MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620

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1 The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may change only on a positive-going Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the master-slave construction of this device. P D = 460 mw typ/pkg (No Load) f toggle = 10 MHz (typ) t r, t f =.0 ns typ (0% 0%) LOGIC DIAGRAM CDIP 16 L SUFFIX CASE 60 PDIP 16 P SUFFIX CASE 64 MARKING DIAGRAMS MC10176L AWLYYWW MC10176P AWLYYWW 1 PLCC 0 FN SUFFIX CASE AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE C D Q n+1 L X Q n H* L L H* H H *A clock H is a clock transition from a low to a high state. Pin assignment is for Dual in Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 1 of the ON Semiconductor MECL Data Book (DL1/D). ORDERING INFORMATION Device Package Shipping MC10176L CDIP 16 Units / Rail MC10176P PDIP 16 Units / Rail MC10176FN PLCC 0 46 Units / Rail Semiconductor Components Industries, LLC, 00 January, 00 Rev. 7 1 Publication Order Number: MC10176/D

2 ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Limits Pin Under 30 C + C + C Test Min Max Min Typ Max Min Max Unit Power Supply Drain Current I E madc Input Current I inh I inl Output Voltage Logic 1 V OH 1 Output Voltage Logic 0 V OL 1 Threshold Voltage Logic 1 V OHA 1 Threshold Voltage Logic 0 V OLA 1 Switching Times (0Ω Load) Clock Input Propagation Delay t ++ t Rise Time (0 to 0%) t Fall Time (0 to 0%) t Setup Time t setup... ns Hold Time t hold ns Toggle Frequency (Max) f tog MHz µadc µadc Vdc Vdc Vdc Vdc ns Output level to be measured after a clock pulse has been applied to the C Input (Pin )

3 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Test Temperature V IHmax V ILmin V IHAmin V ILAmax V EE Symbol 30 C C C Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under (V CC ) Test V IHmax V ILmin V IHAmin V ILAmax V EE Gnd Power Supply Drain Current I E Input Current I inh I inl Output Voltage Logic 1 V OH 1 Output Voltage Logic 0 V OL 1 Threshold Voltage Logic 1 V OHA 1 Threshold Voltage Logic 0 V OLA 1 1 Switching Times (0Ω Load) +1.11Vdc +0.31V Pulse In Pulse Out 3. V +.0 V Clock Input Propagation Delay t ++ t + Rise Time (0 to 0%) t +, Fall Time (0 to 0%) t, Setup Time t setup, Hold Time t hold, Toggle Frequency (Max) f tog 1 1,, 1 Output level to be measured after a clock pulse has been applied to the C Input (Pin ) Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 00 linear fpm is maintained. Outputs are terminated through a 0 ohm resistor to.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. 3

4 PACKAGE DIMENSIONS PLCC 0 FN SUFFIX PLASTIC PLCC PACKAGE CASE 77 0 ISSUE C B N Y BRK U D L M Z W D X G1 V VIEW D D Z A R K1 H C G G1 E J T VIEW S VIEW S K F 4

5 PACKAGE DIMENSIONS T F A E G D 16 PL B C N CDIP 16 L SUFFIX CERAMIC DIP PACKAGE CASE ISSUE T K L M J 16 PL H A G B F C S K D 16 PL T PDIP 16 P SUFFIX PLASTIC DIP PACKAGE CASE 64 0 ISSUE R J L M

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