74HCT32. Quad 2 Input OR Gate with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

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1 Quad 2 Input OR Gate with STT Compatible Inputs igh Performance Silicon Gate CMOS The 74CT32 is identical in pinout to the S32. The device has TT compatible inputs. Features Output Drive Capability: 0 STT oads TT/NMOS Compatible Input evels Outputs Directly Interface to CMOS, NMOS and TT Operating Voltage Range: 4.5 to 5.5 V ow Input Current:.0 A igh Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements ESD Performance: BM 2000 V; Machine Model 200 V Chip Complexity: 48 FETs or 2 Equivalent Gates These are Pb Free Devices SOIC 4 D SUFFIX CASE 75A TSSOP 4 DT SUFFIX CASE 948G MARKING DIAGRAMS 4 CT32G AWYWW CT 32 AYW CT32 = Device Code A = Assembly ocation, W = Wafer ot Y = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Semiconductor Components Industries, C, 2007 March, 2007 Rev. 0 Publication Order Number: 74CT32/D

2 Pinout: 4 ead Packages (Top View) OGIC DIAGRAM V CC B4 A4 Y4 B3 A3 Y A B 2 3 Y A B Y A2 B2 Y2 GND FUNCTION TABE Inputs Output A2 B2 A3 B3 A4 B PIN 4 = V CC PIN 7 = GND 6 Y2 Y = A+B 8 Y3 Y4 A B Y ORDERING INFORMATION Device Package Shipping 74CT32DR2G SOIC 4 (Pb Free) 2500 / Tape & Reel 74CT32DTR2G TSSOP 4* For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit V CC DC Supply Voltage (Referenced to GND) 0.5 to V V in DC Input Voltage (Referenced to GND) 0.5 to V CC V V out DC Output Voltage (Referenced to GND) 0.5 to V CC V I in DC Input Current, per Pin ±20 ma I out DC Output Current, per Pin ±25 ma I CC DC Supply Current, V CC and GND Pins ±50 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package T stg Storage Temperature 65 to + 50 C T ead Temperature, mm from Case for 0 Seconds SOIC or TSSOP Package 260 mw C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GND (V in or V out ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor igh Speed CMOS Data Book (D29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V CC DC Supply Voltage (Referenced to GND) V V in, V out DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time V CC = V (Figure ) V CC = 4.5 V V CC = 6.0 V ns 3

4 DC CARACTERISTICS (Voltages Referenced to GND) Guaranteed imit V CC Symbol Parameter Condition (V) 55 to 25 C 85 C 25 C Unit V I Minimum igh evel Input Voltage V out = 0.V I out 20 A V I Maximum ow evel Input Voltage V out = V CC 0.V I out 20 A V O V O Minimum igh evel Output Voltage Maximum ow evel Output Voltage V in = V I I out 20 A V in = V I I out 4.0mA V in = V I I out 20 A V in = V I I out 4.0mA I in Maximum Input eakage Current V in = V CC or GND 5.5 ±0. ±.0 ±.0 A I CC I CC Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current V in = V CC or GND I out = 0 A V in = 2.4V, Any One Input V in = V CC or GND, Other Inputs I out = 0 A A 55 C 25 to 25 C Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor igh Speed CMOS Data Book (D29/D). 2. Total Supply Current = I CC + Σ I CC. V V V V ma AC CARACTERISTICS (C = 50pF, Input t r = t f = 6ns) Guaranteed imit V CC Symbol Parameter (V) 55 to 25 C 85 C 25 C Unit t P, t P Maximum Propagation Delay, Input A or B to Output Y (Figures and 2) ns t T, t T Maximum Output Transition Time, Any Output (Figures and 2) ns C in Maximum Input Capacitance pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor igh Speed CMOS Data Book (D29/D). 25 C, V CC = 5.0 V, V EE = 0 V C PD Power Dissipation Capacitance (Per Buffer)* 20 pf * Used to determine the no load dynamic power consumption: P D = C PD V 2 CC f + I CC V CC. For load considerations, see Chapter 2 of the ON Semiconductor igh Speed CMOS Data Book (D29/D). 4

5 t r t f INPUT A OR B 90% 50% 0% V CC GND t P t P OUTPUT Y 90% 50% 0% t T t T Figure. Switching Waveforms TEST POINT DEVICE UNDER TEST OUTPUT C * *Includes all probe and jig capacitance Figure 2. Test Circuit A B Y Figure 3. Expanded ogic Diagram (/4 of the Device) 5

6 PACKAGE DIMENSIONS SOIC 4 CASE 75A 03 ISSUE T SEATING PANE G A 4 8 D 4 P 7 B K P 7 P C 0.25 (0.00) M T B S A S 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOERANCING PER ANSI Y4.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.27 (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. MIIMETERS INCES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.27 BSC BSC J K M P R SODERING FOOTPRINT* 4X X X PITC DIMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 6

7 PACKAGE DIMENSIONS TSSOP 4 CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PANE U U S 2X /2 PIN IDENT. S D C 4 4X K REF 0.0 (0.004) M T U S V S N (0.00) M B U 7 A V G N J J F DETAI E K K ÇÇÇ ÉÉÉ SECTION N N DETAI E W NOTES:. DIMENSIONING AND TOERANCING PER ANSI Y4.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS, PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC J J K K BSC BSC M SODERING FOOTPRINT* PITC 4X X.26 DIMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 7

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