MC74VHC08. Quad 2-Input AND Gate

Transcription

1 M7408 Quad 2-Input ND Gate The M7408 is an advanced high speed MOS 2 input ND gate fabricated with silicon gate MOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining MOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0, allowing the interface of 5.0 systems to 3.0 systems. Features igh Speed: t PD = 4.3 ns (Typ) at = 5.0 ow Power Dissipation: I = (Max) at T = 25 igh Noise Immunity: NI = NI = 28% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for to 5.5 Operating Range ow Noise: OP = 0.8 (Max) Pin and Function ompatible with Other Standard ogic Families atchup Performance Exceeds 300 m ESD Performance: uman Body Model > 2000 ; Machine Model > 200 hip omplexity: 24 FETs or 6 Equivalent Gates These Devices are Pb Free and are RoS ompliant B 2 B2 3 B3 4 B Figure. ogic Diagram 3 Y 6 Y2 8 Y3 Y4 B4 4 Y4 B3 3 Y Y = B 4 4 SOI 4 D SUFFIX SE 75 TSSOP DT SUFFIX SE 948G MRKING DIGRMS = ssembly ocation W, = Wafer ot Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNTION TBE Inputs Output B Y 08 YW ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet G WYWW B Y 2 B2 Y2 GND (Top iew) Figure 2. Pinout: 4 ead Packages Semiconductor omponents Industries,, 204 September, 204 Rev. 9 Publication Order Number: M7408/D

2 M7408 MXIMUM RTINGS Symbol Parameter alue Unit D Supply oltage 0.5 to +7.0 in D Input oltage 0.5 to +7.0 out D Output oltage 0.5 to +0.5 I IK Input Diode urrent 20 m I OK Output Diode urrent ±20 m I out D Output urrent, per Pin ±25 m I D Supply urrent, and GND Pins ±50 m P D Power Dissipation in Still ir, SOI Package ÎÎ 500 TSSOP Package 450 mw T stg Storage Temperature 65 to +50 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating SOI Package: 7 mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 REOMMENDED OPERTING ONDITIONS Symbol Parameter ÎÎ Min Max Unit D Supply oltage 5.5 in D Input oltage out D Output oltage 0 T Operating Temperature t r, t f Input Rise and Fall Time = 3.3 ± ns/ ÎÎ = 5.0 ± Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. D EETRI RTERISTIS Î T = 25 T = 55 to 25 Symbol Parameter Test onditions Min Typ Max Min Max Unit I Minimum igh evel ÎÎ Input oltage 3.0 to 5.5 x 0.7 x I ÎÎ Maximum ow evel Î Input oltage 3.0 to x x 0.3 O ÎÎ Minimum igh evel Î in = I or I.9 Î.9 Output oltage I O = Î 4.4 in = I or I I O = 4.0 m I O = 8.0 m Î 3.80 O ÎÎ Maximum ow evel Î in = I or I Î 0.0 Output oltage Î I O = Î ÎÎ in = I or I I O = 4.0 m I O = 8.0 m I in ÎÎ Maximum Input Î in = 5.5 or GND 0 to 5.5 ±0. ±.0 eakage urrent I ÎÎ Maximum Quiescent in = or GND 5.5 Supply urrent Î This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions.

3 M7408 EETRI RTERISTIS (Input t r = t f = 3.0 ns) T = 25 ÎÎ T = 55 to 25 Î Symbol Parameter Test onditions Min Typ Max Min Max Unit t P, ÎÎ Maximum Propagation = 3.3 ± 0.3 = 5 pf Î 6.2 Î t P ÎÎ Delay, = 50 pf Î ns or B to Y = 5.0 ± 0.5 = 5 pf Î = 50 pf ÎÎ in Maximum Input pf apacitance PD Power Dissipation apacitance (Note ) 25, = 5.0. PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. verage operating current can be obtained by the equation: I (OPR) = PD f in + I / 4 (per gate). PD is used to determine the no load dynamic power consumption; P D = PD 2 f in + I. 8 pf NOISE RTERISTIS (Input t r = t f = 3.0 ns, = 50 pf, = 5.0 ) T = 25 Symbol haracteristic Typ Max Unit OP Quiet Output Maximum Dynamic O O Quiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage.5 TEST POINT or B t P 50% t P GND DEIE UNDER TEST OUTPUT * Y 50% Figure 3. Switching Waveforms *Includes all probe and jig capacitance Figure 4. Test ircuit INPUT Figure 5. Input Equivalent ircuit ORDERING INFORMTION M7408DR2G M7408DTR2G Device Package Shipping SOI 4 (Pb Free) TSSOP 4 (Pb Free) 2500 Units / Tape & Reel 2500 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 3

4 M7408 PKGE DIMENSIONS SOI 4 SE ISSUE J T SETING PNE G 4 8 D 4 P 7 B K P 7 P 0.25 (0.00) M T B S S 0.25 (0.00) M B M NOTES:. DIMENSIONING ND TOERNING PER NSI Y4.5M, ONTROING DIMENSION: MIIMETER. 3. DIMENSIONS ND B DO NOT INUDE MOD PROTRUSION. 4. MXIMUM MOD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INUDE DMBR PROTRUSION. OWBE DMBR PROTRUSION S BE 0.27 (0.005) TOT IN EXESS OF TE D DIMENSION T MXIMUM MTERI ONDITION. MIIMETERS INES R X 45 F DIM MIN MX MIN MX B D M J F G.27 BS BS J K M P R SODERING FOOTPRINT 4X X X PIT DIMENSIONS: MIIMETERS 4

5 M7408 PKGE DIMENSIONS SOI 4 SE ISSUE K M B M e D 7 3X b B E 0.25 M S B S SETING PNE DETI h X 45 M 3 DETI NOTES:. DIMENSIONING ND TOERNING PER SME Y4.5M, ONTROING DIMENSION: MIIMETERS. 3. DIMENSION b DOES NOT INUDE DMBR PROTRUSION. OWBE PROTRUSION S BE 0.3 TOT IN EXESS OF T MXIMUM MTERI ONDITION. 4. DIMENSIONS D ND E DO NOT INUDE MOD PROTRUSIONS. 5. MXIMUM MOD PROTRUSION 0.5 PER SIDE. MIIMETERS INES DIM MIN MX MIN MX b D E e.27 BS BS h M SODERING FOOTPRINT* X.8.27 PIT 4X 0.58 DIMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 5

6 M7408 PKGE DIMENSIONS TSSOP 4 SE 948G ISSUE B 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SETING PNE U U S 2X /2 PIN IDENT. S D 4 G 4X K REF 0.0 (0.004) M T U S S 8 7 B U N N J J F DETI E DETI E 0.25 (0.00) K K M ÇÇÇ ÉÉÉ SETION N N SODERING FOOTPRINT W NOTES:. DIMENSIONING ND TOERNING PER NSI Y4.5M, ONTROING DIMENSION: MIIMETER. 3. DIMENSION DOES NOT INUDE MOD FS, PROTRUSIONS OR GTE BURRS. MOD FS OR GTE BURRS S NOT EXEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INUDE INTERED FS OR PROTRUSION. INTERED FS OR PROTRUSION S NOT EXEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INUDE DMBR PROTRUSION. OWBE DMBR PROTRUSION S BE 0.08 (0.003) TOT IN EXESS OF TE K DIMENSION T MXIMUM MTERI ONDITION. 6. TERMIN NUMBERS RE SOWN FOR REFERENE ONY. 7. DIMENSION ND B RE TO BE DETERMINED T DTUM PNE W. MIIMETERS INES DIM MIN MX MIN MX B D F G 0.65 BS BS J J K K BS BS M PIT 4X X.26 DIMENSIONS: MIIMETERS ON Semiconductor and the are registered trademarks of Semiconductor omponents Industries, (SI) or its subsidiaries in the United States and/or other countries. SI owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SI s product/patent coverage may be accessed at Marking.pdf. SI reserves the right to make changes without further notice to any products herein. SI makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SI assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SI data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SI does not convey any license under its patent rights nor the rights of others. SI products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SI product could create a situation where personal injury or death may occur. Should Buyer purchase or use SI products for any such unintended or unauthorized application, Buyer shall indemnify and hold SI and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SI was negligent regarding the design or manufacture of the part. SI is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBITION ORDERING INFORMTION ITERTURE FUFIMENT: iterature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 8027 US Phone: or Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative M7408/D