NB3N2304NZ. 3.3V 1:4 Clock Fanout Buffer

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1 3.3V 1:4 lock Fanout Buffer Description The NB3N2304NZ is a low skew 1 to 4 clock fanout buffer, designed for high speed clock distribution such as in PI X applications. The NB3N2304NZ guarantees low output to output skew. Optimal design, layout and processing minimizes skew within a device and from device to device. The Output Enable (OE) pin forces the outputs LOW when LOW. Features Input/Output lock Frequency up to 140 MHz Low Skew Outputs (100 ps) Output Enable Operating Range: V DD = 3.0 V to 3.6 V Ideal for PI X and networking clocks Packaged in 8 pin TSSOP, 4.4 mm x 3 mm Industrial Temperature Range These are Pb Free Devices* DT SUFFIX SE 948S 1 DFN8 MN SUFFIX SE 506 MRKING DIGRM* 40N YWW 6O M 1 4 Y WW M = ssembly Location = Year = Work Week = Date ode = Pb Free Package *For additional marking information, refer to pplication Note ND8002/D. Figure 1. Simplified Logic Diagram ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor omponents Industries, LL, 2009 October, 2009 Rev. 6 1 Publication Order Number: NB3N2304NZ/D

2 OE Logic ontrol IN 1 8 Q4 Q1 OE 2 7 Q3 IN Q2 Q3 Q1 GND V DD Q2 Q4 Figure 2. Block Diagram Figure 3. NB3N2304NZ Package Pinout (Top View) Table 1. PIN DESRIPTION Pin Pin # Name Type Description 1 IN LVMOS/LVTTL Input lock Input 2 OE LVMOS/LVTTL Input Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs are forced to logic LOW when OE is forced LOW. 3 Q1 LVMOS/LVTTL Output lock Output 1 4 GND Power Negative Supply Voltage; onnect to Ground, 0 V 5 Q2 (LV)MOS/(LV)TTL Input lock Output 2 6 V DD Power Positive Supply Voltage (3.0 V to 3.6 V) 7 Q3 (LV)MOS/(LV)TTL Output lock Output 3 8 Q4 (LV)MOS/(LV)TTL Input lock Output 4 EP Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 2. OE, ENBLE FUNTION TBLE Inputs Outputs IN OE L L L H L L L H L H H H 2

3 Table 3. TTRIBUTES ESD Protection haracteristics Human Body Model Machine Model Value > 2kV > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) DFN 8 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V in Transistor ount Meets or exceeds JEDE Spec EI/JESD78 I Latchup Test 1. For additional information, see pplication Note ND8003/D. 480 Devices Table 4. MXIMUM RTINGS Symbol Parameter ondition 1 ondition 2 Rating Unit V DD Positive Power Supply GND = 0 V V DD + 0.5V V V I Input Voltage GND 0.5 V I V DD V T Operating Temperature Range, Industrial 40 to +85 T stg Storage Temperature Range 65 to +150 J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm 0 lfpm 500 lfpm DFN 8 DFN 8 T SOL Wave Solder Pb Free (Note 2) 265 J Thermal Resistance (Junction to ase) (Note 2) DFN8 35 to 40 /W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability. 2. JEDE standard multilayer board 2S2P (2 signal, 2 power) /W 3

4 Table 5. D HRTERISTIS V DD = 3.0 V to 3.6 V, GND = 0 V, T = 40 to +85 Symbol haracteristic Min Typ Max Unit I DD Power Supply MHz, Unloaded Outputs m V OH Output HIGH Voltage IOH = 24 m IOH = 12 m V V OL Output LOW Voltage IOL = 24 m IOL = 12 m V V IH Input HIGH Voltage, IN and OE (Note 3) 2.0 V V IL Input LOW Voltage, IN and OE (Note 3) 0.8 V I IH Input HIGH urrent, V IN = V DD I IL Input LOW urrent, V IN = 0 V IN Input apacitance, IN, OE 5 7 pf NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. IN input has a threshold voltage of V DD /2. Table 6. HRTERISTIS V DD = 3.0 V to 3.6 V, GND = 0 V, T = 40 to +85 (Note 4) (Figure 4) Symbol haracteristic Min Typ Max Unit f in Input lock Frequency D 140 MHz t Dskew Duty ycle Skew = t2 t1 (Figure 4) Measured at 1.5 V % tr/tf Output Rise and Fall Times; 0.8 V to 2.0 V L = 25 pf L = 10 pf ns t pd Propagation Delay, IN to Qn (Note 5) ns t skew Output to Output Skew; (Note 5) 100 ps t pu Powerup Time for V DD to Reach Minimum Specified Voltage ms NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. ll outputs loaded equally with L = 25 pf to GND. Duty cycle out = duty in F decoupling capacitor should be connected between V DD and GND. 5. Measured on rising edges at V DD 2; all outputs with equal loading. 4

5 Duty ycle Timing t 2 t V 1.5 V 1.5 V ll Outputs Rise/Fall Time 2.0 V 2.0 V 0.8 V 0.8 V t r t f 3.3 V 0 V Output Output Skew 1.5 V 1.5 V t SKEW Input Output Propagation Delay INPUT V DD /2 V DD /2 t pd Figure 4. Switching Waveforms ORDERING INFORMTION Device Package Shipping NB3N2304NZDTG (Pb Free) 100 Units / Rail NB3N2304NZDTR2G (Pb Free) 2500 / Tape & Reel NB3N2304NZMNR4G* DFN8 (Pb Free) 1000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *ontact a sales representative. 5

6 PKGE DIMENSIONS SE 948S 01 ISSUE 0.20 (0.008) T 0.20 (0.008) T L U U (0.003) T SETING PLNE S PIN 1 IDENT S D 2X L/ x V K REF (0.004) M T U S V S G B U J N DETIL E N ÉÉÉÉ ÇÇÇ J1 K1 K SETION N N 0.25 (0.010) M W NOTES: 1. DIMENSIONING ND TOLERNING PER NSI Y14.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION DOES NOT INLUDE MOLD FLSH. PROTRUSIONS OR GTE BURRS. MOLD FLSH OR GTE BURRS SHLL NOT EXEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INLUDE INTERLED FLSH OR PROTRUSION. INTERLED FLSH OR PROTRUSION SHLL NOT EXEED 0.25 (0.010) PER SIDE. 5. TERMINL NUMBERS RE SHOWN FOR REFERENE ONLY. 6. DIMENSION ND B RE TO BE DETERMINED T DTUM PLNE -W-. MILLIMETERS INHES DIM MIN MX MIN MX B D F G 0.65 BS BS J J K K L 6.40 BS BS M F DETIL E 6

7 PKGE DIMENSIONS DFN8 SE ISSUE D PIN ONE REFERENE D B NOTES: 1. DIMENSIONING ND TOLERNING PER SME Y14.5M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b PPLIES TO PLTED TERMINL ND IS MESURED BETWEEN 0.25 ND 0.30 MM FROM TERMINL. 4. OPLNRITY PPLIES TO THE EXPOSED PD S WELL S THE TERMINLS. 2 X X 0.10 ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ TOP VIEW E MILLIMETERS DIM MIN MX REF b D 2.00 BS D E 2.00 BS E e 0.50 BS K 0.20 L X SETING PLNE SIDE VIEW (3) D2 e/ X L e E2 K X b B NOTE 3 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLITION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 5163, Denver, olorado US Phone: or Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB3N2304NZ/D