NB3L553/D. 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer

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Marshall Harmon
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2.5 V / 3.3 V / 5.0 V :4 Clock Fanout Buffer Description The is a low skew to 4 clock fanout buffer, designed for clock distribution in mind. The specifically guarantees low output to output skew.

1 2.5 V / 3.3 V / 5.0 V :4 Clock Fanout Buffer Description The is a low skew to 4 clock fanout buffer, designed for clock distribution in mind. The specifically guarantees low output to output skew. Optimal design, layout and processing minimize skew within a device and from device to device. Features Input/Output Clock Frequency up to 200 MHz Low Skew Outputs (35 ps), Typical RMS Phase Jitter (2 khz 20 MHz): 29 fs (Typical) Output goes to Three State Mode via OE Operating Range: V DD = V to 5.25 V 5 V Tolerant Input Clock I CLK Ideal for Networking Clocks Packaged in pin SOIC Industrial Temperature Range These are Pb Free Devices I CLK OE Q Q2 Q3 Q4 Figure. Block Diagram 3L553 L Y W MRKING DIGRMS* SOIC D SUFFIX CSE 75 = Specific Device Code = ssembly Location = Wafer Lot = Year = Work Week = Pb Free Package DFN MN SUFFIX CSE 506 PINOUT DIGRM V DD OE 2 7 Q0 Q3 3 6 Q Q2 4 5 GND I CLK 3L553 LYW 6P M 6P = Specific Device Code M = Date Code = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to pplication Note ND002/D. ORDERING INFORMTION Device Package Shipping DG DR2G SOIC (Pb Free) SOIC (Pb Free) 9 Units/Rail 2500/Tape & Reel MNR4G* DFN (Pb Free) 000/Tape & Reel *Contact Sales Representative For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD0/D. Semiconductor Components Industries, LLC, 202 July, 202 Rev. Publication Order Number: /D

2 Table. OE, OUTPUT ENBLE FUNCTION OE Function 0 Disable Enable Table 2. PIN DESCRIPTION Pin # Name Type Description V DD Power Positive supply voltage (2.375 V to 5.25 V) 2 Q0 (LV)CMOS/(LV)TTL Output Clock Output 0 3 Q (LV)CMOS/(LV)TTL Output Clock Output 4 GND Power Negative supply voltage; Connect to ground, 0 V 5 I CLK (LV)CMOS Input Clock Input. 5.0 V tolerant 6 Q2 (LV)CMOS/(LV)TTL Output Clock Output 2 7 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3 OE (LV)TTL Input V DD for normal operation. Pin has no internal pullup or pull down resistor for open condition default. Use from to 0 kohms external resistor to force an open condition default state. EP Thermal Exposed Pad (DFN only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. 2

3 Table 3. MXIMUM RTINGS Symbol Parameter Condition Condition 2 Rating Unit V DD Positive Power Supply GND = 0 V 6.0 V V I Input Voltage OE I CLK GND = 0 V and V DD = V to 5.25 V GND 0.5 V I V DD GND 0.5 V I 5.75 V T Operating Temperature Range, Industrial 40 to +5 C T stg Storage Temperature Range 65 to +50 C J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm SOIC C/W C/W JC Thermal Resistance (Junction to Case) (Note ) SOIC 4 to 44 C/W J Thermal Resistance (Junction to mbient) 0 lfpm 500 lfpm DFN DFN 29 4 C/W C/W JC Thermal Resistance (Junction to Case) (Note ) DFN 35 to 40 C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. JEDEC standard multilayer board 2S2P (2 signal, 2 power) Table 4. TTRIBUTES ESD Protection Characteristic Human Body Model Machine Model Charged Device Model Value > 2 kv > 50 V > TBD kv Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Level Flammability Rating Oxygen Index: 2 to 34 UL 94 code V 0.25 in Transistor Count 53 Devices Meets or Exceeds JEDEC Standard EI/JESD7 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to pplication Note ND003/D. 3

4 Table 5. DC CHRCTERISTICS (V DD = V to V, GND = 0 V, T = 40 C to +5 C) (Note 3) Symbol Characteristic Min Typ Max Unit I DD Power Supply 35 MHz, No Load m V OH Output HIGH Voltage I OH = 6 m.7 V V OL Output LOW Voltage I OL = 6 m 0.4 V V IH, I CLK Input HIGH Voltage, I CLK (V DD 2) V V IL, I CLK Input LOW Voltage, I CLK (V DD 2) 0.5 V V IH, OE Input HIGH Voltage, OE. V DD V V IL, OE Input LOW Voltage, OE 0.7 V ZO Nominal Output Impedance 20 CIN Input Capacitance, I CLK, OE 5.0 pf IOS Short Circuit Current ± 2 m DC CHRCTERISTICS (V DD = 3.5 V to 3.45 V, GND = 0 V, T = 40 C to +5 C) (Note 3) Symbol Characteristic Min Typ Max Unit I DD Power Supply 35 MHz, No Load m V OH Output HIGH Voltage I OH = 25 m 2.4 V V OL Output LOW Voltage I OL = 25 m 0.4 V V OH Output HIGH Voltage I OH = 2 m (CMOS level) V DD 0.4 V V IH, I CLK Input HIGH Voltage, I CLK (V DD 2) V V IL, I CLK Input LOW Voltage, I CLK (V DD 2) 0.7 V V IH, OE Input HIGH Voltage, OE 2.0 V DD V V IL, OE Input LOW Voltage, OE 0 0. V ZO Nominal Output Impedance 20 CIN Input Capacitance, OE 5.0 pf IOS Short Circuit Current ± 50 m DC CHRCTERISTICS (V DD = 4.75 V to 5.25 V, GND = 0 V, T = 40 C to +5 C) (Note 3) Symbol Characteristic Min Typ Max Unit I DD Power Supply 35 MHz, No Load 45 5 m V OH Output HIGH Voltage I OH = 35 m 2.4 V V OL Output LOW Voltage I OL = 35 m 0.4 V V OH Output HIGH Voltage I OH = 2 m (CMOS level) V DD 0.4 V V IH, I CLK Input HIGH Voltage, I CLK (V DD 2) V V IL, I CLK Input LOW Voltage, I CLK (V DD 2) V V IH, OE Input HIGH Voltage, OE 2.0 V DD V V IL, OE Input LOW Voltage, OE 0. V ZO Nominal Output Impedance 20 CIN Input Capacitance, OE 5.0 pf IOS Short Circuit Current ± 0 m 4

5 Table 6. C CHRCTERISTICS; V DD = 2.5 V 5% (V DD = V to V, GND = 0 V, T = 40 C to +5 C) (Note 3) Symbol Characteristic Min Typ Max Unit f in Input Frequency 200 MHz t r /t f Output rise and fall times; 0. V to 2.0 V.0.5 ns t pd Propagation Delay, CLK to Q n (Note 4) ns t skew Output to output skew; (Note 5) ps t skew Device to device skew, (Note 5) 500 ps C CHRCTERISTICS; V DD = 3.3 V 5% (V DD = 3.5 V to 3.45 V, GND = 0 V, T = 40 C to +5 C) (Note 3) Symbol Characteristic Conditions Min Typ Max Unit f in Input Frequency 200 MHz t jitter ( ) RMS Phase Jitter (Integrated 2 khz 20 MHz) (See Figures 2 and 3) f carrier = 00 MHz fs t r /t f Output rise and fall times; 0. V to 2.0 V ns t pd Propagation Delay, CLK to Q n (Note 4) ns t skew Output to output skew; (Note 5) ps t skew Device to device skew, (Note 5) 500 ps C CHRCTERISTICS; V DD = 5.0 V 5% (V DD = 4.75 V to 5.25 V, GND = 0 V, T = 40 C to +5 C) (Note 3) Symbol Characteristic Min Min Typ Max Unit f in Input Frequency 200 MHz t jitter ( ) RMS Phase Jitter (Integrated 2 khz 20 MHz) (See Figures 2 and 3) f carrier = 00 MHz 29 fs t r /t f Output rise and fall times; 0. V to 2.0 V ns t pd Propagation Delay, CLK to Q n (Note 4) ns t skew Output to output skew; (Note 5) ps t skew Device to device skew, (Note 5) 500 ps 3. Outputs loaded with external R L = 33 series resistor and C L = 5 pf to GND. Duty cycle out = duty in. 0.0 F decoupling capacitor should be connected between V DD and GND. 4. Measured with rail to rail input clock 5. Measured on rising edges at V DD 2 between any two outputs with equal loading. 5

The RMS phase jitter contributed by the device (integrated between 2 khz to 20 MHz; as shown in the shaded area) is fs (RMS Phase Jitter of the input source is 75.40 fs and Output (DUT+Source) is 93.

6 Figure 2. Phase Noise Plot at 00 MHz at an Operating Voltage of 3.3 V, Room Temperature The above plot captured using gilent E5052 shows dditive Phase Noise of the device measured with an input source generated by gilent E663B. The RMS phase jitter contributed by the device (integrated between 2 khz to 20 MHz; as shown in the shaded area) is fs (RMS Phase Jitter of the input source is fs and Output (DUT+Source) is 93.6 fs). Figure 3. Phase Noise Plot at 00 MHz at an Operating Voltage of 5 V, Room Temperature The above plot captured using gilent E5052 shows dditive Phase Noise of the device measured with an input source generated by gilent E663B. The RMS phase jitter contributed by the device (integrated between 2 khz to 20 MHz; as shown in the shaded area) is 29 fs (RMS Phase Jitter of the input source is fs and Output (DUT+Source) is 03.5 fs). 6

7 PCKGE DIMENSIONS X B Y Z H G D 5 4 S C 0.25 (0.00) M Z Y S X S 0.25 (0.00) M SETING PLNE Y 0.0 (0.004) M SOIC NB CSE ISSUE K N X 45 M SOLDERING FOOTPRINT* K J NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION ND B DO NOT INCLUDE MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DMBR PROTRUSION. LLOWBLE DMBR PROTRUSION SHLL BE 0.27 (0.005) TOTL IN EXCESS OF THE D DIMENSION T MXIMUM MTERIL CONDITION THRU RE OBSOLETE. NEW STNDRD IS MILLIMETERS INCHES DIM MIN MX MIN MX B C D G.27 BSC BSC H J K M 0 0 N S SCLE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 PCKGE DIMENSIONS 2X PIN ONE REFERENCE 2X C 0.0 C C D ÇÇ ÇÇ TOP VIEW B 0.0 C (3) NOTE 4 SETING SIDE VIEW C PLNE DETIL DETIL B D2 4 E X L E2 L DFN 2x2, 0.5P CSE ISSUE E EXPOSED Cu L DETIL OPTIONL CONSTRUCTIONS ÉÉ MOLD CMPD DETIL B OPTIONL CONSTRUCTION L PCKGE OUTLINE NOTES:. DIMENSIONING ND TOLERNCING PER SME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b PPLIES TO PLTED TERMINL ND IS MESURED BETWEEN 0.5 ND 0.20 MM FROM TERMINL TIP. 4. COPLNRITY PPLIES TO THE EXPOSED PD S WELL S THE TERMINLS. MILLIMETERS DIM MIN MX REF b D 2.00 BSC D E 2.00 BSC E e 0.50 BSC K 0.30 REF L L 0.0 RECOMMENDED SOLDERING FOOTPRINT*.30 X 0.50 K e/2 e 5 BOTTOM VIEW X b 0.0 C 0.05 C B NOTE X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 027 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative /D

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