MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
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1 The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive going Clock transition. Thus, outputs may change only on a positive going Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the master slave construction of this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET ONLY FUNCTIONS WHEN CLOCK IS LOW. P D = 460 mw typ/pkg (No Load) f toggle = 0 MHz (typ) t r, t f =.0 ns typ (0% 0%) LOGIC DIAGRAM CDIP L SUFFIX CASE 60 PDIP P SUFFIX CASE 64 MARKING DIAGRAMS MC06L AWLYYWW MC06P AWLYYWW PLCC 0 FN SUFFIX CASE AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE R C D Qn + L L X Q n L H* L L L H* H H H L X L *A clock H is a clock transition from a low to a high state. Pin assignment is for Dual in Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page of the ON Semiconductor MECL Data Book (DL/D). ORDERING INFORMATION Device Package Shipping MC06L CDIP Units / Rail MC06P PDIP Units / Rail MC06FN PLCC 0 46 Units / Rail Semiconductor Components Industries, LLC, 00 January, 00 Rev. 7 Publication Order Number: MC06/D
2 MC06 ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Limits Pin Under 30 C + C + C Test Min Max Min Typ Max Min Max Unit Power Supply Drain Current I E 0 madc Input Current I inh 9 Output Voltage Logic V OH Output Voltage Logic 0 V OL Threshold Voltage Logic V OHA Threshold Voltage Logic 0 V OLA Switching Times (0Ω Load) Propagation Delay t +3 t +4 t 9++ t µadc I inl µadc Rise Time (0 to 0%) t Fall Time (0 to 0%) t Setup Time t setup.... ns Hold Time t hold.... ns Toggle Frequency (Max) f tog 0 MHz Vdc Vdc Vdc Vdc ns Output level to be measured after clock pulse. appears at clock input (Pin 9).
3 MC06 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Test Temperature V IHmax V ILmin V IHAmin V ILAmax V EE Symbol 30 C C C Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under (V CC ) Test V IHmax V ILmin V IHAmin V ILAmax V EE Gnd Power Supply Drain Current I E Input Current I inh 9 Output Voltage Logic V OH Output Voltage Logic 0 V OL Threshold Voltage Logic V OHA Threshold Voltage Logic 0 V OLA 9 I inl Switching Times (0Ω Load) +.Vdc +0.3V Pulse In Pulse Out 3. V +.0 V Propagation Delay t +3 t +4 t 9++ t Rise Time (0 to 0%) t +, 9 Fall Time (0 to 0%) t, 9 Setup Time t setup, 9 Hold Time t hold, 9 Toggle Frequency (Max) f tog 6 7, 9, 9, 9, Output level to be measured after clock pulse. appears at clock input (Pin 9). Each MECL 0,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 00 linear fpm is maintained. Outputs are terminated through a 0 ohm resistor to.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. 3
4 MC06 PACKAGE DIMENSIONS PLCC 0 FN SUFFIX PLASTIC PLCC PACKAGE CASE 77 0 ISSUE C B N Y BRK U D L M Z W D X G V VIEW D D Z A R K H C G G E J T VIEW S VIEW S K F 4
5 MC06 PACKAGE DIMENSIONS T F A E G D PL B C N CDIP L SUFFIX CERAMIC DIP PACKAGE CASE 60 0 ISSUE T K L M J PL H A G B F C S K D PL T PDIP P SUFFIX PLASTIC DIP PACKAGE CASE 64 0 ISSUE R J L M
6 MC06 Notes 6
7 MC06 Notes 7
8 MC06 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 3, Denver, Colorado 07 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: 00 9 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4 3 Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r4@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. MC06/D
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