7SB3125. Bus Switch. The 7SB3125 Bus Switch is an advanced high speed line switch in ultra small footprint.

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7S32 us Switch The 7S32 us Switch is an advanced high speed line switch in ultra small footprint. Features High Speed: t PD = 0.2 ns (Max) @ V =.

1 7S32 us Switch The 7S32 us Switch is an advanced high speed line switch in ultra small footprint. Features High Speed: t PD = 0.2 ns V =. V 3 Switch onnection etween 2 Ports Power Down Protection Provided on Inputs Ultra Small Packages These are Pb Free Devices OE SOT 33/S70 /S 88 DF SUFFIX SE 9 MRKING DIGRMS H M Figure. Logic Diagram OE 2 V OE 2 V N SOT23 /TSOP /S9 DT SUFFIX SE 83 E M GND 3 Figure 2. TSOP /S 88 (Top View) GND 3 Figure 3. ULLG/UDFN (Top View) ULLG.0 x.0 SE 3D F M Function Table Input OE L Function = ULLG.2 x.0 SE 3E M H Disconnect ULLG. x.0 SE 3F M UDFN.2 x.0 SE 7 M J H, E, F,,, J = Specific Device ode M = Date ode = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor omponents Industries, LL, 200 September, 200 Rev. Publication Order Number: 7S32/D

2 7S32 Table. MXIMUM RTINGS Symbol Parameter Value Unit V D Supply Voltage 0. to +7.0 V V IN ontrol Pin Input Voltage 0. to +7.0 V V I/O Switch Input / Output Voltage 0. to +7.0 V I IK ontrol Pin D Input Diode urrent V IN < GND 0 m I OK Switch I/O Port D Diode urrent V I/O < GND 0 m I O On State Switch urrent ±28 m ontinuous urrent Through V or GND ±0 m I D Supply urrent per Supply Pin ±0 m I GND D Ground urrent per Ground Pin ±0 m T STG Storage Temperature Range to +0 T L Lead Temperature, mm from ase for 0 Seconds 20 T J Junction Temperature Under ias 0 J Thermal Resistance S70 /S 88 (Note ) TSOP ULLG/UDFN P D Power Dissipation in Still ir at 8 S70 /S 88 (Note ) TSOP ULLG/UDFN MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 28 to 3 UL 9 V 0.2 in /W mw V ESD ESD Withstand Voltage Human ody Mode (Note 2) Machine Mode (Note 3) harged Device Mode (Note ) >2000 >200 N/ V I LTHUP Latchup Performance bove V and elow GND at 8 (Note ) ±00 m Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability.. Measured with minimum pad spacing on an FR board, using 0 mm by inch, 2 ounce copper trace no air flow. 2. Tested to EI/ JESD22 3. Tested to EI/ JESD22. Tested to JESD22 0. Tested to EI / JESD78. Table 2. REOMMENDED OPERTING ONDITIONS Symbol Parameter Min Max Unit V Positive D Supply Voltage.0. V V I ontrol Pin Input Voltage 0. V V I/O Switch Input / Output Voltage 0. V T Operating Free ir Temperature +2 t / V Input Transition Rise or Fall Rate ontrol Input Switch I/O 0 0 D ns/v 2

3 7S32 Table 3. D ELETRIL HRTERISTIS Symbol Parameter onditions V (V) T = 2 T = to +2 Min Typ Max Min Max V IK lamp Diode Voltage I IN = 8 m..2.2 V V IH High Level Input Voltage (ontrol).0 to V Unit V IL Low Level Input Voltage (ontrol).0 to V I IN Input Leakage urrent 0 V IN. V. ±0. ±.0 I OFF Power Off Leakage urrent V I/O = 0 to. V 0 ±0. ±.0 I Quiescent Supply urrent I O = 0, V IN = V or 0 V I Increase in Supply urrent (ontrol Pin) One input at 3. V; Other inputs at V or GND R ON Switch ON Resistance V I/O = 0, I I/O = m I I/O = 30 m. ±0. ± m V I/O = 2., I I/O = m V I/O = 2., I I/O = m Table. ELETRIL HRTERISTIS Symbol Parameter V (V) Test ondition t PD Propagation Delay, to or to T = 2 T = to +2 Min Typ Max Min Max.0 to. See Figure ns t EN Output Enable Time. to ns t DIS Output Disable Time. to ns IN ontrol Input apacitance.0 V IN = 3 V or pf IO(ON) Switch On apacitance.0 Switch ON 0 pf IO(OFF) Switch Off apacitance.0 Switch OFF 3. pf Unit 3

4 7S32 Loading and Waveforms From Output Under Test L = 0 pf (see Note ) S 7 V Open GND TEST t PD t PLZ /t PZL t PHZ /t PZH S Open 7 V GND LOD IRUIT Output ontrol. V. V 3 V 0 V Input. V. V 3 V 0 V Output Waveform S at 7 V (see Note ) t PZL. V t PLZ V OL V 3. V V OL Output t PHL t PLH. V. V VOLTGE WVEFORMS PROPGTION DELY TIMES V OH V OL Output Waveform 2 S at Open (see Note ) t PZH. V t PHZ VOLTGE WVEFORMS ENLE ND DISLE TIMES V OH V OH 0.3 V 0 V. L includes probe and jig capacitance.. Waveform is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.. ll input pulses are supplied by generators having the following characteristics: PRR 0 MHz, Z O = 0, t r 2. ns, t f 2. ns. D. The output is measured with one input transition per measurement. E. t PLZ and t PHZ are the same as t dis. F. t PZL and t PZH are the same as t en. G. t PLH and t PHL are the same as t pd. Figure. Load ircuit and Voltage Waveforms DEVIE ORDERING INFORMTION Device Package Shipping 7S32DTTG TSOP 7S32DFT2G 7S32MXTG 7S32MXTG 7S32MXTG S 88 ULLG 0. mm Pitch ULLG 0. mm Pitch ULLG 0.3 mm Pitch 7S32MUTG UDFN 0. mm Pitch For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications rochure, RD80/D.

5 7S32 PKGE DIMENSIONS S G 2 3 D PL S 88, SOT 33, S 70 SE 9 02 ISSUE J 0.2 (0.008) M M N. DIMENSIONING ND TOLERNING PER NSI Y.M, ONTROLLING DIMENSION: INH OSOLETE. NEW STNDRD DIMENSIONS ND DO NOT INLUDE MOLD FLSH, PROTRUSIONS, OR GTE URRS. INHES MILLIMETERS DIM MIN MX MIN MX D G 0.02 S 0. S H J K N REF 0.20 REF S J H K

6 7S32 PKGE DIMENSIONS 2X 2X NOTE 0.0 T 0.20 T L H G D X 0.20 T S SETING PLNE J TSOP SE ISSUE H K DETIL Z M DETIL Z. DIMENSIONING ND TOLERNING PER SME Y.M, ONTROLLING DIMENSION: MILLIMETERS. 3. MXIMUM LED THIKNESS INLUDES LED FINISH THIKNESS. MINIMUM LED THIKNESS IS THE MINIMUM THIKNESS OF SE MTERIL.. DIMENSIONS ND DO NOT INLUDE MOLD FLSH, PROTRUSIONS, OR GTE URRS.. OPTIONL ONSTRUTION: N DDITIONL TRIMMED LED IS LLOWED IN THIS LOTION. TRIMMED LED NOT TO EXTEND MORE THN 0.2 FROM ODY. MILLIMETERS DIM MIN MX 3.00 S.0 S D G 0.9 S H J K L.2. M 0 0 S SOLDERING FOOTPRINT* SLE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

7 7S32 PKGE DIMENSIONS UDFN.2x.0, 0.P SE 7 0 ISSUE 2X 0X PIN ONE REFERENE 0.0 2X L2 D ÉÉÉ TOP VIEW SIDE VIEW 3 E (3) X L L EXPOSED u SETING PLNE DETIL ottom View (Optional) ÉÉÉ DETIL Side View (Optional) EDGE OF PKGE MOLD MPD 3. DIMENSIONING ND TOLERNING PER SME Y.M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b PPLIES TO PLTED TERMINL ND IS MESURED ETWEEN 0.2 ND 0.30 mm FROM TERMINL.. OPLNRITY PPLIES TO THE EXPOSED PD S WELL S THE TERMINLS. MILLIMETERS DIM MIN MX REF b D.20 S E.00 S e 0.0 S L L L MOUNTING FOOTPRINT* b NOTE 3 e OTTOM VIEW 0.0 PITH.07 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 7S32 PKGE DIMENSIONS PIN ONE REFERENE D ÉÉ TOP VIEW E ULLG.0x.0, 0.3P SE 3D 0 ISSUE. DIMENSIONING ND TOLERNING PER SME Y.M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b PPLIES TO PLTED TERMINL ND IS MESURED ETWEEN 0. ND 0.30 mm FROM THE TERMINL TIP.. MXIMUM OF 0.0 PULL K OF THE PLTED TERMINL FROM THE EDGE OF THE PKGE IS LLOWED. MILLIMETERS DIM MIN MX b D.00 S E.00 S e 0.3 S L L SIDE VIEW SETING PLNE MOUNTING FOOTPRINT SOLDERMSK DEFINED* X L 3 e X L NOTE.8 OTTOM VIEW b NOTE PKG OUTLINE 0.3 PITH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8

9 7S32 PKGE DIMENSIONS ULLG.2x.0, 0.P SE 3E 0 ISSUE PIN ONE REFERENE L D ÉÉ ÉÉ TOP VIEW SIDE VIEW 3 e E SETING PLNE X L NOTE. DIMENSIONING ND TOLERNING PER SME Y.M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b PPLIES TO PLTED TERMINL ND IS MESURED ETWEEN 0. ND 0.30 mm FROM THE TERMINL TIP.. MXIMUM OF 0.0 PULL K OF THE PLTED TERMINL FROM THE EDGE OF THE PKGE IS LLOWED. MILLIMETERS DIM MIN MX b D.20 S E.00 S e 0.0 S L L MOUNTING FOOTPRINT SOLDERMSK DEFINED* X OTTOM VIEW b NOTE PKG OUTLINE 0.0 PITH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 9

10 7S32 PKGE DIMENSIONS ULLG.x.0, 0.P SE 3F 0 ISSUE PIN ONE REFERENE D ÉÉÉ ÉÉÉ TOP VIEW SIDE VIEW E SETING PLNE. DIMENSIONING ND TOLERNING PER SME Y.M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b PPLIES TO PLTED TERMINL ND IS MESURED ETWEEN 0. ND 0.30 mm FROM THE TERMINL TIP.. MXIMUM OF 0.0 PULL K OF THE PLTED TERMINL FROM THE EDGE OF THE PKGE IS LLOWED. MILLIMETERS DIM MIN MX b D. S E.00 S e 0.0 S L L MOUNTING FOOTPRINT SOLDERMSK DEFINED* X L 3 e X L NOTE.2 OTTOM VIEW b NOTE PKG OUTLINE 0.0 PITH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should uyer purchase or use SILL products for any such unintended or unauthorized application, uyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PULITION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. ox 3, Denver, olorado 8027 US Phone: or Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative 7S32/D

MC74VHC1G05. Single Inverter with Open Drain Output

MC74VHC1G05. Single Inverter with Open Drain Output Single Inverter with Open Drain Output The is an advanced high speed MOS inverter with open drain output fabricated with silicon gate MOS technology. The internal circuit is composed of three stages, including