2 Input NAND Gate L74VHC1G00

Transcription

1 Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. The input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the to be used to interface 5 V circuits to 3 V circuits. High Speed: t PD = 3.0 ns (Typ) at V CC = 5 V Low Power Dissipation: I CC = ma (Max) at T A = 5 C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families 5 MARKING DIAGRAMS 3 SC 70/SC 88A/SOT 353 DF SUFFIX V d 5 Pin d = Date Code Figure. Pinout (Top View) 3 SOT 3/TSOP 5/SC 59 DT SUFFIX V d Pin d = Date Code Figure. Logic Symbol PIN ASSIGNMENT IN B IN A 3 GND OUT Y 5 V CC FUNCTION TABLE Inputs Output A B Y L L H L H H H L H H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. /6

2 MAXIMUM RATINGS Symbol Parameter Value Unit V CC DC Supply Voltage 0.5 to V V IN DC Input Voltage 0.5 to V CC V V OUT DC Output Voltage 0.5 to V CC V I IK DC Input Diode Current ± 0 ma I OK DC Output Diode Current ± 0 ma I OUT DC Output Sink Current ±.5 ma I CC DC Supply Current per Supply Pin ± 5 ma T STG Storage Temperature Range 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds 60 C T J Junction Temperature Under Bias + 50 C θ JA Thermal Resistance SC 70/SC 88A (Note ) 50 C/W TSOP 5 00 P D Power Dissipation in Still Air at 85C SC 70/SC 88A 50 mw TSOP 5 30 MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 30% 35% UL 9 V 0 (0.5 in) V ESD ESD Withstand Voltage Human Body Model (Note ) >000 V Machine Model (Note 3) > 00 Charged Device Model (Note ) N/A I LATCH UP Latch Up Performance Above V CC and Below GND at 85C (Note 5) ± 500 ma Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.. Measured with minimum pad spacing on an FR board, using 0 mm by inch, ounce copper trace with no air flow.. Tested to EIA/JESD A A. 3. Tested to EIA/JESD A5 A.. Tested to JESD C0 A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V CC DC Supply Voltage V V IN DC Input Voltage V V OUT DC Output Voltage 0.0 V CC V T A Operating Temperature Range C t r,t f Input Rise and Fall Time V CC = 3.3 ± 0.3 V 0 00 ns/v V CC = 5.0 ± 0.5 V 0 0 DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.% BOND FAILURES Junction Time, Time, Temperature C Hours Years 80,03, , , , , , ,900.0 NORMALIZED FAILURE RATE TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature /6

3 DC ELECTRICAL CHARACTERISTICS V CC T A = 5 C T A < 85 C 55 C to 5 C Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit V IH Minimum High Level V Input Voltage V IL Maximum Low Level V Input Voltage V OH Minimum High Level V IN = V IH or V IL V Output Voltage I OH = 50 µa V IN = V IH or V IL V IN = V IH or V IL I OH = ma I OH = 8 ma V OL Maximum Low Level V IN = V IH or V IL V Output Voltage I OL = 50 µa V IN = V IH or V IL V IN = V IH or V IL I OL = ma I OL = 8 ma I IN Maximum Input V IN = 5.5 V or GND 0 to5.5 ±0. ±.0 ±.0 µa Leakage Current I CC Maximum Quiescent V IN = V CC or GND µa Supply Current AC ELECTRICAL CHARACTERISTICS C load = 50 pf, Input t r = t f = 3.0 ns T A = 5 C T A < 85 C 55 C<T A <5 C Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit t PLH, Maximum V CC = 3.3± 0.3 V C L = 5 pf ns t PHL Propagation Delay, C L = 50 pf Input A or B to Y V CC = 5.0± 0.5 V C L = 5 pf C L = 50 pf C IN Maximum Input pf Capacitance 5 C, V CC = 5.0 V C PD Power Dissipation Capacitance (Note 6) 0 pf 6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD V CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD V CC f in + I CC V CC. Figure. Switching Waveforms *Includes all probe and jig capacitance. A MHz square input wave is recommended for propagation delay tests. Figure 5. Test Circuit 3/6

4 DEVICE ORDERING INFORMATION Device Nomenclature Package Type Device Order Tape and Logic Temp (Name/SOT#/ Device Package Tape and Number Reel Size Circuit Range Technology Common Name) Function Suffix Reel Suffix Indicator Identifier DFT L 7 VHCG 00 DF T SC 70/SC 88A/ 78 mm (7 in) SOT Unit DFT L 7 VHCG 00 DF T SC 70/SC 88A/ 78 mm (7 in) SOT Unit DTT L 7 VHCG 00 DT T SOT 3/TSOP 5/ 78 mm (7 in) SC Unit /6

5 A G PACKAGE DIMENSIONS SC70 5/SC 88A/SOT 353 DF SUFFIX NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: INCH. 3. 9A 0 OBSOLETE. NEW STANDARD 9A 0.. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. S 5 B 3 D 5 PL 0. (0.008) M B M N INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D G 0.06 BSC 0.65 BSC H J K N REF 0.0 REF S C J H K SOLDERING FOOTPRINT* SCALE 0: mm inches 5/6

6 PACKAGE DIMENSIONS SOT3 5/TSOP 5/SC59 5 DT SUFFIX 0.05 (0.00) S H D 5 3 L G A B C K J M NOTES:. DIMENSIONING AND TOLERAG PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.. A AND B DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G H J K L M 0 _ 0 _ 0 _ 0 _ S SOLDERING FOOTPRINT* SCALE 0: mm inches 6/6