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1 Is Now Part of To learn more about ON Semiconductor, please visit our website at ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor omponents Industries, LL dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON Semiconductor s product/patent coverage may be accessed at ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. uyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should uyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, uyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

2 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Features 0.8 V to.6 V V Supply Operation.6 V Over-Voltage Tolerant I/Os at V from 0.8V to.6 V Extremely High Speed tpd -. ns: Typical at. V Power-Off High-Impedance Inputs and Outputs Low Static Power onsumption - I =0.9 µ Maximum Low Dynamic Power onsumption - PD =.0 pf Typical at. V Ultra-Small MicroPak Packages Ordering Information Description September 01 The 74UP1G6 is a universal, configurable, two-input logic gate with an open drain that provides a highperformance and low-power solution for batterypowered portable applications. This product is designed for a wide low-voltage operating range (0.8 V to.6 V) and guarantees very low static and dynamic power consumption across the entire voltage range. ll inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. The 74UP1G6 provides for multiple functions, as determined by various configurations of the three inputs. The potential logic functions provided are ND, NND, OR, NOR, XNOR, inverter, and buffer (see Figure through Figure 8). Part Number Top Mark Package Packing Method 74UP1G6L6X K 6-Lead, MicroPak, 1.0 mm Wide 000 Units on Tape & Reel 74UP1G6FHX K 6-Lead, MicroPak, 1x1 mm ody,. mm Pitch 000 Units on Tape & Reel 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) 008 Fairchild Semiconductor orporation 74UP1G6 Rev. 1.0.

3 Pin onfiguration Pin Definitions Function Table GND V Figure 1. MicroPak (Top Through View) Pin # Name Description 1 Data Input GND Ground Data Input 4 Output (Open Drain) V Supply Voltage 6 Data Input Inputs =Output L L L H (1) L L H L L H L H (1) L H H L H L L L H L H L H H L H (1) H H H H (1) H = HIGH Logic Level L = LOW Logic Level Note: 1. High impedance output state, open drain. Function Selection Table -Input Logic Function onnection onfiguration -Input ND Figure -Input ND with oth Inputs Inverted Figure -Input NND with Inverted Input Figure, Figure 4 -Input OR with Inverted Input Figure, Figure 4 -Input NOR Figure -Input NOR with oth Inputs Inverted Figure -Input XNOR Figure 6 Inverter Figure 7 uffer Figure 8 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) 008 Fairchild Semiconductor orporation 74UP1G6 Rev. 1.0.

4 Logic onfigurations Figure through Figure 8 show the logical functions that can be implemented using the 74UP1G6. The diagrams show the DeMorgan s equivalent logic duals for a given two-input function. The logical 1 Figure. 6 4 V -Input ND Gate or -Input NOR with oth Inputs Inverted 1 Figure V -Input NND with Inverted Input or -Input OR Gate with Inverted Input 1 Figure 6. -Input XNOR Gate 6 4 V implementation is next to the board-level physical implementation of how the pins should be connected. 1 Figure. Figure V -Input NND with Inverted Input or -Input OR Gate with Inverted Input V -Input NOR Gate or -Input ND Gate with oth Inputs Inverted 1 Figure 7. Inverter 6 4 V 6 4 V 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Figure 8. Non-Inverter uffer 008 Fairchild Semiconductor orporation 74UP1G6 Rev. 1.0.

5 bsolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V Supply Voltage V V IN D Input Voltage V V OUT D Output Voltage () V I IK D Input Diode urrent V IN < 0V -0 m I OK D Output Diode urrent V OUT < 0V -0 m I OL D Output Sink urrent +0 m I or I GND D V or Ground urrent per Supply Pin ±0 m T STG Storage Temperature Range T J Junction Temperature Under ias +10 T L Junction Lead Temperature, Soldering 10s +60 P D ESD Power Dissipation at +8 MicroPak MicroPak Human ody Model, JEDE:JESD harged Device Model, JEDE:JESD Note:. I O absolute maximum rating must be observed. Recommended Operating onditions () The Recommended Operating onditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to bsolute Maximum Ratings. Symbol Parameter ondition Min. Max. Unit V Supply Voltage V V IN Input Voltage 0.6 V V OUT Output Voltage V =0 V 0.6 V I OL Output urrent V =.0 V to.6 V 4.0 V =. V to.7 V.1 V =1.6 V to 1.9 V 1.9 V =1.4 V to 1.6 V 1.7 V =1.1 V to 1. V 1.1 mw V =0.8 V 0.0 µ T Operating Temperature, Free ir θ J Thermal Resistance MicroPak MicroPak Note:. Unused inputs must be held HIGH or LOW. They may not float. V m /W 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) 008 Fairchild Semiconductor orporation 74UP1G6 Rev

6 D Electrical haracteristics Symbol Parameter V ondition V P V N V H V OL I IN I OFF ΔI OFF I Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage LOW Level Output Voltage Input Leakage urrent Power Off Leakage urrent dditional Power Off Leakage urrent Quiescent Supply urrent T = T =-40 to 8 Min. Max. Min. Max V.60 I OL =0 µ V 1.0 I OL =1.1 m 0.0 x V 0.0 x V 1.40 V 1.60 I OL =1.7 m V 1.9 I OL =1.9 m V.70 I OL =.1 m V.60 I OL =4.0 m V to.6 V 0 V IN.6 V ±0.1 ±0. µ 0 V 0 (V IN,V O ).6 V µ 0V to 0. V 0.8V to.6 V V IN or V O = 0 V to.6 V Unit µ V IN - V or GND V V IN.6 V ±0.9 V V V V µ 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) ΔI Increase in I per Input. V V IN =V -0.6 V µ 008 Fairchild Semiconductor orporation 74UP1G6 Rev. 1.0.

7 Electrical haracteristics Symbol Parameter V ondition T = T =-40 to 8 Unit Min. Typ. Max. Min. Max t PZL, t PLZ 1.10 V L =1 pf, Propagation 1.40 V 1.60 R U =R D = KΩ Delay 1.6 V 1.9 V I = x (V ) (see Figure 9).0 V ns IN OUT PD Input apacitance Output apacitance Power Dissipation apacitance.00 V pf pf V V 1.60 V IN =0 V or V,. 1.6 V 1.9 f=10 MHz.4.0 V V pf 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) 008 Fairchild Semiconductor orporation 74UP1G6 Rev

8 Loadings and Waveforms Notes: 4. L includes load and stray capacitance.. Input PRR = 1.0 MHz, t W = 00 ns. Figure 9. Symbol Figure 10. Test ircuit Waveforms V. V ± 0. V. V ± 0. V 1.8 V ± 0.1 V 1. V ± 0.10 V 1. V ± 0.10 V 0.8 V V mi V / V / V / V / V / V / V x V OL + 0. V V OL V V OL V V OL V V OL V V OL V 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) 008 Fairchild Semiconductor orporation 74UP1G6 Rev

9 Physical Dimensions X 0.0 Notes: 0.0 PIN 1 IDENTIFIER DETIL (0.0) 6X 0.MX 1.4 TOP VIEW OTTOM VIEW X ONFORMS TO JEDE STNDRD M0- VRITION UD. DIMENSIONS RE IN MILLIMETERS. DRWING ONFORMS TO SME 14.M FILENME ND REVISION: M06REV4. PIN ONE IDENTIFIER IS X LENGTH OF N OTHER LINE IN THE MRK ODE LOUT. Figure 11. (0.4) 6X (0.49) X (0.) 1X PIN X X (0.1) 4X 0.07 X 4 HMFER 6-Lead, MicroPak, 1.0 mm Wide (1) (0.0) 6X REOMMENED LND PTTERN X (0.7) DETIL PIN 1 TERMINL Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Package Designator Tape Section avity Number avity Status over Type Status Leader (Start End) 1 (Typical) Empty Sealed L6X arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 008 Fairchild Semiconductor orporation 74UP1G6 Rev

10 Physical Dimensions X X NOTES: 0.0 PIN 1 MIN 0uM (0.08) 4X DETIL OMPLIES TO JEDE MO- STNDRD. DIMENSIONS RE IN MILLIMETERS.. DIMENSIONS ND TOLERNES PER SME 14.M, 1994 D. LNDPTTERN REOMMENDTION IS SED ON FS DESIGN. E. DRWING FILENME ND REVISION: MGF06REV Figure TOP VIEW SIDE VIEW 6 4 OTTOM VIEW 0.MX (0.08) 4X X 0.0 6X X X 0.4 X 0. 1X X4 HMFER (0.0) 6X X X 0.66 REOMMENDED LND PTTERN FOR SPE ONSTRINED P LTERNTIVE LND PTTERN FOR UNIVERSL PPLITION DETIL PIN 1 LED SLE: X 6-Lead, MicroPak, 1x1 mm ody,. mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: 74UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Package Designator Tape Section avity Number avity Status over Type Status Leader (Start End) 1 (Typical) Empty Sealed FHX arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 008 Fairchild Semiconductor orporation 74UP1G6 Rev

11 008 Fairchild Semiconductor orporation 74UP1G6 Rev UP1G6 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output)

12 ON Semiconductor and are trademarks of Semiconductor omponents Industries, LL dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON Semiconductor s product/patent coverage may be accessed at Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. uyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should uyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, uyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PULITION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution enter for ON Semiconductor 191 E. nd Pkwy, urora, olorado US Phone: or Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com Semiconductor omponents Industries, LL N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative

13 Mouser Electronics uthorized Distributor lick to View Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: 74UP1G6FHX 74UP1G6L6X