NTD4965N. Power MOSFET. 30 V, 68 A, Single N Channel, DPAK/IPAK

Transcription

1 NTD96N Power MOSFET V, 68, Single N hannel, DPK/IPK Features Low R DS(on) to Minimize onduction Losses Low apacitance to Minimize Driver Losses Optimized Gate harge to Minimize Switching Losses Three Package Variations for Design Flexibility These Devices are Pb Free, alogen Free/BFR Free and are RoS ompliant pplications PU Power Delivery D D onverters V (BR)DSS R DS(ON) MX I D MX.7 V V 68 V D MXIMUM RTINGS ( unless otherwise stated) Parameter Symbol Value Unit Drain to Source Voltage V DSS V Gate to Source Voltage V GS ± V ontinuous Drain T = I D 17.8 urrent R J T = 1.6 Power Dissipation R J ontinuous Drain urrent R J (Note ) Power Dissipation R J (Note ) ontinuous Drain urrent R J Power Dissipation R J Pulsed Drain urrent Steady State T = P D.6 W T = I D 1. T = 9. T = P D 1.9 W T = I D 68 T = 8 T = P D 8. W t p = s T = I DM 8 urrent Limited by Package T = I DmaxPkg 76 Operating Junction and Storage T J, to Temperature T STG +17 Source urrent (Body Diode) I S Drain to Source dv/dt dv/dt 6. V/ns Single Pulse Drain to Source valanche Energy (, V DD = V, V GS = V, I L = 1 pk, L =.1 m, R G = Lead Temperature for Soldering Purposes (1/8 from case for s) ES 7 mj T L 6 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability. 1. Surface mounted on FR board using 1 sq in pad, 1 oz u.. Surface mounted on FR board using the minimum recommended pad size. 1 Drain YWW 9 6NG G 1 Drain Gate Source S N NNEL MOSFET SE 69 DPK (Bent Lead) STYLE MRKING DIGRMS & PIN SSIGNMENTS Drain YWW 9 6NG Drain YWW 9 6NG 1 Gate Drain Source 1 Gate Drain Source Y = Year WW = Work Week 96N = Device ode G = Pb Free Package 1 SE 69D IPK (Straight Lead DPK) ORDERING INFORMTION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. 1 SE 69 IPK (Straight Lead) Semiconductor omponents Industries, LL, 1 ugust, 1 Rev. 1 Publication Order Number: NTD96N/D

2 NTD96N TERML RESISTNE MXIMUM RTINGS Parameter Symbol Value Unit Junction to ase (Drain) R J.9 /W Junction to TB (Drain) R J TB. Junction to mbient Steady State (Note ) R J 7.6 Junction to mbient Steady State (Note ) R J 7.6. Surface mounted on FR board using 1 sq in pad, 1 oz u.. Surface mounted on FR board using the minimum recommended pad size. ELETRIL RTERISTIS ( unless otherwise specified) Parameter Symbol Test ondition Min Typ Max Unit OFF RTERISTIS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = V Drain to Source Breakdown Voltage Temperature oefficient V (BR)DSS / T J 1. mv/ Zero Gate Voltage Drain urrent I DSS V GS = V, V DS = V 1. T J = 1 Gate to Source Leakage urrent I GSS V DS = V, V GS = ± V ± n ON RTERISTIS (Note ) Gate Threshold Voltage V GS(T) V GS = V DS, I D = V Negative Threshold Temperature oefficient V GS(T) /T J.1 Drain to Source On Resistance R DS(on) V GS = V I D =..7 I D = 1. V GS =. V I D =. I D = 1. Forward Transconductance g FS V DS = 1. V, I D = S RGES, PITNES ND GTE RESISTNE Input apacitance ISS 17 Output apacitance OSS V GS = V, f = 1. Mz, V DS = 1 V 66 Reverse Transfer apacitance RSS Total Gate harge Q G(TOT) 17. Threshold Gate harge Q G(T).7 Gate to Source harge Q GS V GS =. V, V DS = 1 V, I D =.1 Gate to Drain harge Q GD 8. Total Gate harge Q G(TOT) V GS = V, V DS = 1 V, I D = 8. n SWITING RTERISTIS (Note 6) Turn On Delay Time t d(on) Rise Time t r V GS =. V, V DS = 1 V,. Turn Off Delay Time t d(off) I D = 1, R G = Fall Time t f 1.. Pulse Test: pulse width s, duty cycle %. 6. Switching characteristics are independent of operating junction temperatures. 7. ssume terminal length of 1 mils. 1.1 mv/ m pf n ns

3 NTD96N ELETRIL RTERISTIS ( unless otherwise specified) Parameter Symbol Test ondition Min Typ Max Unit SWITING RTERISTIS (Note 6) Turn On Delay Time t d(on) 8. Rise Time t r V GS = V, V DS = 1 V, 1. Turn Off Delay Time t d(off) I D = 1, R G =.. ns Fall Time t f 7.8 DRIN SOURE DIODE RTERISTIS Forward Diode Voltage V SD VGS = V, I S = T J = 1.7 V Reverse Recovery Time t RR 8. harge Time t a V GS = V, dis/dt = / s, 1. ns Discharge Time t b I S = 1 Reverse Recovery harge Q RR 16 n PKGE PRSITI VLUES Source Inductance (Note 7) L S.8 n Drain Inductance, DPK L D.16 Drain Inductance, IPK (Note 7) L D T = 1.88 Gate Inductance (Note 7) L G.9 Gate Resistance R G 1... Pulse Test: pulse width s, duty cycle %. 6. Switching characteristics are independent of operating junction temperatures. 7. ssume terminal length of 1 mils. ORDERING INFORMTION NTD96NTG Device Package Shipping DPK (Pb Free) / Tape & Reel NTD96N 1G IPK (Pb Free) 7 Units / Rail NTD96N G IPK Trimmed Lead (Pb Free) 7 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D.

4 NTD96N TYPIL PERFORMNE URVES 9 8 V thru. V V GS =.7 V 9 8 V DS = V I D, DRIN URRENT () 7 6. V. V.1 V.9 V I D, DRIN URRENT () V 1 T J = 1 T J = 1 V DS, DRIN TO SOURE VOLTGE (V) V GS, GTE TO SOURE VOLTGE (V) Figure 1. On Region haracteristics Figure. Transfer haracteristics R DS(on), DRIN TO SOURE RESISTNE (m ) I D = V GS, GTE TO SOURE VOLTGE (V) 9 R DS(on), DRIN TO SOURE RESISTNE (m ) V GS =. V V GS = V. 6 I D, DRIN URRENT () Figure. On Resistance vs. Gate to Source Voltage Figure. On Resistance vs. Drain urrent and Gate Voltage R DS(on), DRIN TO SOURE RESISTNE (NORMLIZED) I D = V GS = V I DSS, LEKGE (n) T J = 1 T J = 1 T J = 8 V GS = V 1 T J, JUNTION TEMPERTURE ( ) Figure. On Resistance Variation with Temperature V DS, DRIN TO SOURE VOLTGE (V) Figure 6. Drain to Source Leakage urrent vs. Voltage

5 NTD96N TYPIL PERFORMNE URVES, PITNE (pf) V GS = V 18 iss oss 6 rss 1 V DS, DRIN TO SOURE VOLTGE (V) Figure 7. apacitance Variation V GS, GTE TO SOURE VOLTGE (V) Q gs Q gd Q T I D = 1 V DD = 1 V V GS = Q G, TOTL GTE RGE (n) Figure 8. Gate to Source and Drain to Source Voltage vs. Total harge t, TIME (ns) V DD = 1 V I D = 1 V GS = V t d(off) t f t r t d(on), SOURE URRENT () 1 V GS = V T J = 1 IS 1 1 R G, GTE RESISTNE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance V SD, SOURE TO DRIN VOLTGE (V) Figure. Diode Forward Voltage vs. urrent ID, DRIN URRENT () s s 1 ms ms 1 V < V GS < V Single Pulse T =.1 RDS(on) LIMIT dc TERML LIMIT PKGE LIMIT V DS, DRIN TO SOURE VOLTGE (V) E S, SINGLE PULSE DRIN TO SOURE VLNE ENERGY (mj) I D = T J, STRTING JUNTION TEMPERTURE ( ) Figure 11. Maximum Rated Forward Biased Safe Operating rea Figure 1. Maximum valanche Energy vs. Starting Junction Temperature

6 NTD96N PKGE DIMENSIONS DPK (SINGLE GUGE) SE 69 1 ISSUE B L L b e E b 1 b D B DETIL c. (.1) M c L GUGE PLNE L L1 DETIL ROTTED 9 W 1 Z SETING PLNE NOTES: 1. DIMENSIONING ND TOLERNING PER SME Y1.M, ONTROLLING DIMENSION: INES.. TERML PD ONTOUR OPTIONL WITIN DI- MENSIONS b, L and Z.. DIMENSIONS D ND E DO NOT INLUDE MOLD FLS, PROTRUSIONS, OR BURRS. MOLD FLS, PROTRUSIONS, OR GTE BURRS SLL NOT EXEED.6 INES PER SIDE.. DIMENSIONS D ND E RE DETERMINED T TE OUTERMOST EXTREMES OF TE PLSTI BODY. 6. DTUMS ND B RE DETERMINED T DTUM PLNE. INES MILLIMETERS DIM MIN MX MIN MX b b b c c D E e.9 BS.9 BS L L1.8 REF.7 REF L. BS.1 BS L L. 1.1 Z.1.9 SOLDERING FOOTPRINT* STYLE : PIN 1. GTE. DRIN. SOURE. DRIN SLE :1 mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6

7 NTD96N PKGE DIMENSIONS V B R IPK, STRIGT LED SE 69 1 ISSUE O E NOTES: 1.. DIMENSIONING ND TOLERNING PER NSI Y1.M, ONTROLLING DIMENSION: IN.. SETING PLNE IS ON TOP OF DMBR POSITION.. DIMENSION DOES NOT INLUDE DMBR POSITION OR MOLD GTE. SETING PLNE W F G K J D PL.1 (.) W INES MILLIMETERS DIM MIN MX MIN MX B D E F G.9 BS.9 BS J K R V W.... IPK SE 69D 1 ISSUE V B R E NOTES: 1. DIMENSIONING ND TOLERNING PER NSI Y1.M, ONTROLLING DIMENSION: IN. S T SETING PLNE F 1 G K D PL J.1 (.) M T Z INES MILLIMETERS DIM MIN MX MIN MX B D E F G.9 BS.9 BS J K R S V Z.1.9 STYLE : PIN 1. GTE. DRIN. SOURE. DRIN ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLITION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 16, Denver, olorado 817 US Phone: or 8 86 Toll Free US/anada Fax: or Toll Free US/anada orderlit@onsemi.com N. merican Technical Support: Toll Free US/anada Europe, Middle East and frica Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NTD96N/D