NTMFS4935N. Power MOSFET 30 V, 93 A, Single N Channel, SO 8 FL Features
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1 Power MOSFET 3 V, 93, Single N Channel, SO 8 FL Features Low R S(on) to Minimize Conduction Losses Low Capacitance to Minimize river Losses Optimized Gate Charge to Minimize Switching Losses These evices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant pplications CPU Power elivery, C C Converters MXIMUM RTINGS ( unless otherwise stated) Parameter Symbol Value Unit rain to Source Voltage V SS 3 V Gate to Source Voltage V GS ± V Continuous rain Current R J (Note ) T = C T = C I Power issipation R J (Note ) Continuous rain Current R J s (Note ) Power issipation R J s (Note ) Continuous rain Current R J (Note ) Power issipation R J (Note ) Continuous rain Current R JC (Note ) Power issipation R JC (Note ) Pulsed rain Current Steady State T = C P.63 W T = C I 4 T = C T = C P 8.7 W T = C I 3 T = C 8. T = C P.93 W T C = C I 93 T C = 8 C 9 T C = C P 48 W T = C, t p = s I M 7 Current Limited by Package T = C I max Operating Junction and Storage Temperature T J, T STG to + Source Current (Body iode) I S 44 rain to Source V/T dv/d t 6 V/ns Single Pulse rain to Source valanche Energy, V = 4 V, V GS = V, I L = 47 pk, L =. mh, R G = Lead Temperature for Soldering Purposes (/8 from case for s) C E S mj T L 6 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Surface mounted on FR4 board using sq in pad, oz Cu.. Surface mounted on FR4 board using the minimum recommended pad size. SO 8 FLT LE CSE 488 STYLE Y W ZZ V (BR)SS R S(ON) MX I MX 3 V G (4) 3. V V (,6) S (,,3) N CHNNEL MOSFET S S S G = ssembly Location = Year = Work Week = Lot Traceability 93 MRKING IGRM 493N YWZZ For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR8/. ORERING INFORMTION evice Package Shipping NTMFS493NTG SO 8 FL / NTMFS493NCTG (Pb Free) Tape & Reel NTMFS493NT3G SO 8 FL / NTMFS493NCT3G (Pb Free) Tape & Reel Semiconductor Components Industries, LLC, May, Rev. Publication Order Number: NTMFS493N/
2 THERML RESISTNCE MXIMUM RTINGS Parameter Symbol Value Unit Junction to Case (rain) R JC.6 Junction to mbient Steady State (Note 3) R J 47. Junction to mbient Steady State (Note 4) R J 34.8 Junction to mbient (t s) (Note 3) R J Surface mounted on FR4 board using sq in pad, oz Cu. 4. Surface mounted on FR4 board using the minimum recommended pad size. C/W ELECTRICL CHRCTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHRCTERISTICS rain to Source Breakdown Voltage V (BR)SS V GS = V, I = 3 V rain to Source Breakdown Voltage (transient) V (BR)SSt V GS = V, I (aval) = 9., T case = C, t transient = ns 34 V rain to Source Breakdown Voltage Temperature Coefficient V (BR)SS / T J mv/ C Zero Gate Voltage rain Current I SS V GS = V, V S = 4 V. Gate to Source Leakage Current I GSS V S = V, V GS = ± V ± n ON CHRCTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V S, I =..63. V Negative Threshold Temperature Coefficient V GS(TH) /T J 4. mv/ C rain to Source On Resistance R S(on) V GS = V I = I =.7 V GS = 4. V I = I = 3.7 Forward Transconductance g FS V S =. V, I = 3 S CHRGES, CPCITNCES & GTE RESISTNCE Input Capacitance C ISS Output Capacitance C OSS V GS = V, f = MHz, V S = V 64 7 Reverse Transfer Capacitance C RSS 39 9 Capacitance Ratio C RSS / V GS = V, f = MHz, V S = V.. C ISS Total Gate Charge Q G(TOT) Threshold Gate Charge Q G(TH).6 Gate to Source Charge Q GS V GS = 4. V, V S = V; I = 3. Gate to rain Charge Q G 3. Total Gate Charge Q G(TOT) V GS = V, V S = V; I = nc SWITCHING CHRCTERISTICS (Note 6) Turn On elay Time t d(on) Rise Time t r V GS = 4. V, V S = V, Turn Off elay Time t d(off) I =, R G = Fall Time t f 6.6. Pulse Test: pulse width 3 s, duty cycle %. 6. Switching characteristics are independent of operating junction temperatures. 6.3 m pf nc ns
3 ELECTRICL CHRCTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHRCTERISTICS (Note 6) Turn On elay Time t d(on). Rise Time t r V GS = V, V S = V, 8.7 Turn Off elay Time t d(off) I =, R G = ns Fall Time t f. RIN SOURCE IOE CHRCTERISTICS Forward iode Voltage V S VGS = V,.8. I S = 3.7 V Reverse Recovery Time t RR 44.4 Charge Time t a V GS = V, dis/dt = / s,.6 ns ischarge Time t b I S = 3.8 Reverse Recovery Charge Q RR 4 nc PCKGE PRSITIC VLUES Source Inductance L S.6 nh rain Inductance L. nh Gate Inductance L G T = C.84 nh Gate Resistance R G..4. Pulse Test: pulse width 3 s, duty cycle %. 6. Switching characteristics are independent of operating junction temperatures. 3
4 TYPICL CHRCTERISTICS I, RIN CURRENT () V 7 V V V GS = 4. V 3.8 V 3.6 V 3.4 V 3. V 3. V 3.8 V.6 V.4 V 4 I, RIN CURRENT () V S = V... T J = C V S, RIN TO SOURCE VOLTGE (V) V GS, GTE TO SOURCE VOLTGE (V) Figure. On Region Characteristics Figure. Transfer Characteristics R S(on), RIN TO SOURCE RESISTNCE ( ) V GS (V) Figure 3. On Resistance vs. V GS I = 3 R S(on), RIN TO SOURCE RESISTNCE ( ) V GS = 4. V V GS = V 8 I, RIN CURRENT () 4 Figure 4. On Resistance vs. rain Current and Gate Voltage 6 R S(on), RIN TO SOURCE RES- ISTNCE (NORMLIZE) I = 3 V GS = V 7 I SS, LEKGE (n), V GS = V T J = C T J = 8 C 3 T J, JUNCTION TEMPERTURE ( C) V S, RIN TO SOURCE VOLTGE (V) Figure. On Resistance Variation with Temperature Figure 6. rain to Source Leakage Current vs. Voltage 4
5 TYPICL CHRCTERISTICS C, CPCITNCE (pf) C iss Qgd C oss 4 Qgs 3 V = V V GS = V C I = 3 rss V S, RIN TO SOURCE VOLTGE (V) Figure 7. Capacitance Variation V GS = V V GS, GTE TO SOURCE VOLTGE (V) QT Qg, TOTL GTE CHRGE (nc) Figure 8. Gate to Source and rain to Source Voltage vs. Total Charge 3 t, TIME (ns) V = V I = V GS = V t d(off) t f t r t d(on) I S, SOURCE CURRENT () V GS = V R G, GTE RESISTNCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance V S, SOURCE TO RIN VOLTGE (V) Figure. iode Forward Voltage vs. Current I, RIN CURRENT () V GS V Single Pulse T C = C. R S(on) Limit Thermal Limit Package Limit... V S, RIN TO SOURCE VOLTGE (V) Figure. Maximum Rated Forward Biased Safe Operating rea s s ms ms dc E S, SINGLE PULSE RIN TO SOURCE VLNCHE ENERGY (mj) I = 9 T J, STRTING JUNCTION TEMPERTURE ( C) Figure. Maximum valanche Energy vs. Starting Junction Temperature
6 TYPICL CHRCTERISTICS R(t) ( C/W) uty Cycle = % % % % % %. Single Pulse PULSE TIME (sec) Figure 3. Thermal Response 7 6 GFS (S) I () Figure 4. GFS vs. I 6
7 PCKGE IMENSIONS FN x6,.7p (SO 8FL) CSE 488 ISSUE G. C. C 8X b. C B. c L X 3 4 TOP VIEW SIE VIEW e/. C B X E E ETIL. C c 3 X e ETIL 4 X C SETING PLNE NOTES:. IMENSIONING N TOLERNCING PER SME Y4.M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION N E O NOT INCLUE MOL FLSH PROTRUSIONS OR GTE BURRS. MILLIMETERS IM MIN NOM.9.. b.33.4 c.3.8. BSC E 6. BSC E..8 E 3.4 e.7 BSC G..6 K..3 L..6 L..7 M STYLE : PIN. SOURCE. SOURCE SOLERING FOOTPRINT* 3. SOURCE 4. GTE 3X 4X. RIN.7.7 4X. MX PIN (EXPOSE P) E 4 K L M X X G BOTTOM VIEW X *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORERING INFORMTION LITERTURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 63, enver, Colorado 87 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NTMFS493N/
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