MTD6N15T4G. Power Field Effect Transistor DPAK for Surface Mount. N Channel Enhancement Mode Silicon Gate

Transcription

1 Power Field Effect Transistor DPAK for Surface Mount NChannel EnhancementMode Silicon Gate This Power FET is designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers. Features Silicon Gate for Fast Switching Speeds Low R DS(on).3 Max Rugged SOA is Power Dissipation Limited SourcetoDrain Diode Characterized for Use With Inductive Loads Low Drive Requirement V GS(th) =. V Max Surface Mount Package on 16 mm Tape PbFree Package is Available MAXIMUM RATINGS Rating Symbol Value Unit DrainSource Voltage V DSS 1 Vdc DrainGate Voltage (R GS = 1. M ) V DGR 1 Vdc GateSource Voltage Continuous NonRepetitive (t p s) Drain Current Continuous Drain Current Pulsed V GS ± V GSM ± I D 6. I DM Vdc Vpk Adc V (BR)DSS G R DS(on) MAX 1 V.3 NCHANNEL D 1 3 S CASE 369C DPAK (Surface Mount) STYLE I D MAX 6. A Total Power T C = C Derate above C Total Power T A = C Derate above C (Note 1) P D.16 P D 1..1 W W/ C W W/ C MARKING DIAGRAM & PIN ASSIGNMENTS Drain Total Power T A = C (Note 1) Derate above C (Note ) P D W W/ C YWW T 6N1G Operating and Storage Junction Temperature Range THERMAL CHARACTERISTICS T J, T stg 6 to +1 C Characteristic Symbol Value Unit Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1) JunctiontoAmbient (Note ) R JC R JA R JA C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR board using the minimum recommended pad size.. When surface mounted to an FR board using. sq. in. drain pad size. Y WW 6N1 G 1 Gate Drain 3 Source = Year = Work Week = Device Code = PbFree Package ORDERING INFORMATION Device Package Shipping MTD6N1T DPAK /Tape & Reel MTD6N1TG DPAK (PbFree) /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD11/D. Semiconductor Components Industries, LLC, 13 May, 13 Rev. 1 Publication Order Number: MTD6N1/D

2 ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS DrainSource Breakdown Voltage (V GS = Vdc, I D =. madc) V (BR)DSS 1 Vdc Zero Gate Voltage Drain Current (V DS = Rated V DSS, V GS = Vdc) T J = 1 C GateBody Leakage Current, Forward (V GSF = Vdc, V DS = ) I GSSF 1 nadc GateBody Leakage Current, Reverse (V GSR = Vdc, V DS = ) I GSSR 1 nadc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (V DS = V GS, I D = 1. madc) T J = 1 C I DSS V GS(th). 1. Static DrainSource OnResistance (V GS = 1 Vdc, I D = 3. Adc) R DS(on).3 DrainSource OnVoltage (V GS = 1 Vdc) (I D = 6. Adc) (I D = 3. Adc, T J = 1 C) V DS(on) Forward Transconductance (V DS = 1 Vdc, I D = 3. Adc) g FS. mhos DYNAMIC CHARACTERISTICS Input Capacitance C iss 1 pf Output Capacitance (V DS = Vdc, V GS = Vdc, f = 1. MHz) (See Figure 11) C oss Reverse Transfer Capacitance C rss 1 SWITCHING CHARACTERISTICS* (T J = 1 C) TurnOn Delay Time t d(on) ns Rise Time (V DD = Vdc, I D = 3. Adc, R G = ) t r 1 TurnOff Delay Time (See Figures 13 and 1) t d(off) Fall Time t f 1 Total Gate Charge (V DS =. Rated V DSS, Q g 1 (Typ) 3 nc GateSource Charge I D = Rated I D, V GS = 1 Vdc) Q gs. (Typ) GateDrain Charge (See Figure 1) Q gd 7. (Typ) SOURCEDRAIN DIODE CHARACTERISTICS* Forward OnVoltage Forward TurnOn Time (I S = 6. Adc, di/dt = A/ s, V GS = Vdc) t on Limited by stray inductance Adc Vdc Vdc V SD 1.3 (Typ). Vdc Reverse Recovery Time t rr 3 (Typ) ns 3. Pulse Test: Pulse Width 3 s, Duty Cycle %.. PD, POWER DISSIPATION (WATTS) T C T A T C 7 1 T, TEMPERATURE ( C) Figure 1. Power Derating 1 1

3 TYPICAL ELECTRICAL CHARACTERISTICS V 9 V T J = C V 7 V 6 V V 1 3 V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 V GS(th), GATE THRESHOLD VOLTAGE (VOLTS) V DS = V GS I D = 1 ma T J, JUNCTION TEMPERATURE ( C) Figure. OnRegion Characteristics Figure 3. GateThreshold Voltage Variation With Temperature V DS = 1 V T J = C 1 C - C 6 1 V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) V (BR)DSS, DRAIN-TO-SOURCE BREAKDOWN VOLTAGE (NORMALIZED) V GS = V I D =. ma T J, JUNCTION TEMPERATURE ( C) Figure. Transfer Characteristics Figure. Breakdown Voltage Variation With Temperature R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) V GS = 1 V T J = 1 C C - C 1 16 R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) V GS = 1 V I D = 3 A T J, JUNCTION TEMPERATURE ( C) Figure 6. OnResistance versus Drain Current Figure 7. OnResistance Variation With Temperature 3

4 SAFE OPERATING AREA I D, DRAIN CURRENT (AMPS) ms 1 ms R DS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 s 1 s.1 T C = C. V GS = V SINGLE PULSE V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) dc T J 1 C V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure. Maximum Rated Forward Biased Safe Operating Area FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of C and a maximum junction temperature of 1 C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN69, Transient Thermal ResistanceGeneral Data and Its Use provides detailed instructions. Figure 9. Maximum Rated Switching Safe Operating Area SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 9 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, I DM and the breakdown voltage, V (BR)DSS. The switching SOA shown in Figure is applicable for both turnon and turnoff of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: T J(max) T C R JC r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED).7 D = SINGLE PULSE t, TIME OR PULSE WIDTH (ms) P (pk) Figure 1. Thermal Response t 1 t DUTY CYCLE, D = t 1 /t R JC (t) = r(t) R JC R JC (t) = 6. C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t 1 T J(pk) - T C = P (pk) R JC (t) 1

5 C, CAPACITANCE (pf) 16 1 V DS = T J = C V GS = C iss C oss C rss V GS V DS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Capacitance Variation V GS, GATE SOURCE VOLTAGE (VOLTS) 16 1 T J = C I D = 6 A V DS = V 7 V 1 V Q g, TOTAL GATE CHARGE (nc) 1 16 Figure 1. Gate Charge versus GateToSource Voltage RESISTIVE SWITCHING V DD t on t off PULSE GENERATOR z = V in R L DUT V out t d(on) t r t d(off) t f OUTPUT, V out INVERTED 9% 9% 1% R gen INPUT, V in 1% % 9% % PULSE WIDTH Figure 13. Switching Test Circuit Figure 1. Switching Waveforms

6 PACKAGE DIMENSIONS L3 L b e E b3 1 3 b A D B DETAIL A c. (.13) M C A DPAK (SINGLE GAUGE) CASE 369C ISSUE D C c H L GAUGE PLANE L L1 DETAIL A ROTATED 9 CW SOLDERING FOOTPRINT* A1 H C Z SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.M, CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED.6 INCHES PER SIDE.. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. INCHES MILLIMETERS DIM MIN MAX MIN MAX A A b b b c c D E e.9 BSC.9 BSC H L L1.1 REF.7 REF L. BSC.1 BSC L L. 1.1 Z STYLE : PIN 1. GATE. DRAIN 3. SOURCE. DRAIN SCALE 3:1 mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 163, Denver, Colorado 17 USA Phone: or 336 Toll Free USA/Canada Fax: or 3367 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MTD6N1/D