NCV8402D, NCV8402AD. Dual Self-Protected Low-Side Driver with Temperature and Current Limit

Transcription

1 Dual Self-Protected Low-Side Driver with Temperature and Current Limit NCVD/AD is a dual protected Low Side Smart Discrete device. The protection features include overcurrent, overtemperature, ESD and integrated Drain to Gate clamping for overvoltage protection. This device offers protection and is suitable for harsh automotive environments. Features Short Circuit Protection Thermal Shutdown with Automatic Restart Overvoltage Protection Integrated Clamp for Inductive Switching ESD Protection dv/dt Robustness Analog Drive Capability (Logic Level Input) NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications Switch a Variety of Resistive, Inductive and Capacitive Loads Can Replace Electromechanical Relays and Discrete Circuits Automotive / Industrial V (BR)DSS (Clamped) R DS(ON) TYP I D MAX V 6 V. A* *Max current limit value is dependent on input condition. Gate Input ESD Protection Temperature Limit Overvoltage Protection SO CASE 7 STYLE Current Limit MARKING DIAGRAM xxxxxx = VD or AD A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package PIN ASSIGNMENT Source Drain Gate Drain Source Drain Gate Drain Drain Current Sense Source xxxxxx ALYW ORDERING INFORMATION Device Package Shipping NCVDDRG NCVADDRG SOIC (Pb Free) /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. Semiconductor Components Industries, LLC, 6 July, 6 Rev. 3 Publication Order Number: NCVD/D

2 MAXIMUM RATINGS (T J = C unless otherwise noted) Rating Symbol Value Unit Drain to Source Voltage Internally Clamped V DSS V Drain to Gate Voltage Internally Clamped (R G =. M ) V DGR V Gate to Source Voltage V GS V Continuous Drain Current I D Internally Limited Power T A = C (Note T A = C (Note ) P D..6 W Maximum Continuous Drain T A = C (Note T A = C (Note ) Thermal Resistance Junction to Ambient Steady State (Note ) Junction to Ambient Steady State (Note ) I D.. R JA 7 R JA 77 A C/W Single Pulse Drain to Source Avalanche Energy (V DD = 3 V, V G =. V, I PK =. A, L = 3 mh, R G(ext) = ) E AS mj Load Dump Voltage (V GS = and V, R I =., R L = 9., t d = ms) V LD V Operating Junction and Storage Temperature T J, T stg to C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Surface mounted onto min pad FR PCB, (Cu area = sq. mm, oz.).. Surface mounted onto sq. FR board (Cu area = 6 sq. mm, oz.). I D + DRAIN + I G GATE VDS VGS SOURCE Figure. Voltage and Current Convention

3 ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Parameter Test Condition Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage (Note 3) V GS = V, I D = ma, T J = C V (BR)DSS 6 V V GS = V, I D = ma, T J = C Zero Gate Voltage Drain Current V GS = V, V DS = 3 V, T J = C I DSS.. A V GS = V, V DS = 3 V, T J = C. Gate Input Current V DS = V, V GS =. V I GSSF A ON CHARACTERISTICS (Note 3) Gate Threshold Voltage V GS = V DS, I D = A V GS(th).3.. V Gate Threshold Temperature Coefficient V GS(th) /T J. 6. mv/ C Static Drain to Source On Resistance V GS = V, I D =.7 A, T J = C R DS(on) 6 m V GS = V, I D =.7 A, T J = C 3 V GS =. V, I D =.7 A, T J = C 9 3 V GS =. V, I D =.7 A, T J = C 36 6 V GS =. V, I D =. A, T J = C 9 3 V GS =. V, I D =. A, T J = C 3 6 Source Drain Forward On Voltage V GS = V, I S = 7. A V SD. V SWITCHING CHARACTERISTICS Turn On Delay Time (% V IN to 9% I D ) td(on) 3 s Turn On Rise Time (% I D to 9% I D ) t rise s Turn Off Delay Time (9% V IN to % I D ) V GS = V, V DD = V, td(off) s Turn Off Fall Time (9% I D to % I D ) I D =. A, R L =.7 t fall 7 s Slew Rate ON (7% V DS to % V DD ) dv DS /dt ON.. V s Slew Rate OFF (% V DS to 7% V DD ) dv DS /dt OFF.3. SELF PROTECTION CHARACTERISTICS (T J = C unless otherwise noted) (Note ) Current Limit V DS = V, V GS =. V, T J = C I LIM A V DS = V, V GS =. V, T J = C V DS = V, V GS = V, T J = C... V DS = V, V GS = V, T J = C Temperature Limit (Turn off) V GS =. V T LIM(off) 7 C Thermal Hysteresis V GS =. V T LIM(on) Temperature Limit (Turn off) V GS = V T LIM(off) 6 Thermal Hysteresis V GS = V T LIM(on) GATE INPUT CHARACTERISTICS Device ON Gate Input Current V GS = V I D =. A I GON A V GS = V I D =. A Current Limit Gate Input Current V GS = V, V DS = V I GCL. ma V GS = V, V DS = V. Thermal Limit Fault Gate Input Current V GS = V, V DS = V I GTL. ma V GS = V, V DS = V.7 ESD ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Electro Static Discharge Capability Human Body Model (HBM) ESD V Machine Model (MM) 3. Pulse Test: Pulse Width 3 s, Duty Cycle %. 3

4 . Fault conditions are viewed as beyond the normal operating range of the part.. Not subject to production testing.

5 TYPICAL PERFORMANCE CURVES I L(max) (A) T Jstart = C E max (mj) T Jstart = C T Jstart = C T Jstart = C L (mh) Figure. Single Pulse Maximum Switch off Current vs. Load Inductance L (mh) Figure 3. Single Pulse Maximum Switching Energy vs. Load Inductance T Jstart = C I L(max) (A) T Jstart = C E max (mj) T Jstart = C T Jstart = C. TIME IN CLAMP (ms) Figure. Single Pulse Maximum Inductive Switch off Current vs. Time in Clamp TIME IN CLAMP (ms) Figure. Single Pulse Maximum Inductive Switching Energy vs. Time in Clamp I D (A) T A = C V V 6 V V V 3. V I D (A) 3 V DS = V C C C C 3 V V GS =. V 3 V DS (V) Figure 6. On state Output Characteristics 3 V GS (V) Figure 7. Transfer Characteristics

6 TYPICAL PERFORMANCE CURVES R DS(on) (m ) 3 C, I D =. A C, I D =.7 A C, I D =.7 A C, I D =. A C, I D =.7 A C, I D =. A C, I D =. A C, I D =.7 A V GS (V) Figure. R DS(on) vs. Gate Source Voltage R DS(on) (m ) 3 C, V GS = V 3 C, V GS = V C, V GS = V C, V GS = V C, V GS = V C, V GS = V C, V GS = V C, V GS = V I D (A) Figure 9. R DS(on) vs. Drain Current R DS(on) (NORMALIZED) I D =.7 A V GS = V V GS = V. 6 T ( C) Figure. Normalized R DS(on) vs. Temperature I LIM (A) C C C C V DS = V V GS (V) Figure. Current Limit vs. Gate Source Voltage I LIM (A) V GS = V V GS = V V DS = V 6 T J ( C) Figure. Current Limit vs. Junction Temperature I DSS ( A)... V GS = V C C C C. 3 3 V DS (V) Figure 3. Drain to Source Leakage Current 6

7 TYPICAL PERFORMANCE CURVES NORMALIZED V GS(th) (V) TIME ( s) I D = A V GS = V DS.6 6 T ( C) Figure. Normalized Threshold Voltage vs. Temperature t f t d(on) t d(off) I D =. A V DD = V R G = V GS (V) Figure 6. Resistive Load Switching Time vs. Gate Source Voltage t r V SD (V) DRAIN SOURCE VOLTAGE SLOPE (V/ s)..9. C C C.7 C.6 V GS = V I S (A) Figure. Source Drain Diode Forward Characteristics I D =. A V DD = V R G = dv DS /d t(on) dv DS /d t(off) V GS (V) Figure 7. Resistive Load Switching Drain Source Voltage Slope vs. Gate Source Voltage TIME ( s) 7 I D =. A V DD = V t r, (V GS = V) t d(off), (V GS = V) t f, (V GS = V) t f, (V GS = V) t d(off), (V GS = V) t r, (V GS = V) t d(on), (V GS = V) t d(on), (V GS = V) 6 R G ( ) Figure. Resistive Load Switching Time vs. Gate Resistance DRAIN SOURCE VOLTAGE SLOPE (V/ s)..6. dv DS /d t(off), V GS = V dv DS /d t(on), V GS = V dv DS /d t(off), V GS = V. dv DS /d t(on), V GS = V I D =. A V DD = V R G ( ) Figure 9. Drain Source Voltage Slope during Turn On and Turn Off vs. Gate Resistance 7

8 TYPICAL PERFORMANCE CURVES R(t) ( C/W) Duty Cycle = % % % % % %... Single Pulse PULSE WIDTH (sec) Figure. Transient Thermal Resistance

9 TEST CIRCUITS AND WAVEFORMS RL VIN RG G D DUT VDD + S IDS Figure. Resistive Load Switching Test Circuit 9% VIN td(on) tr td(off) % tf 9% IDS % Figure. Resistive Load Switching Waveforms 9

10 TEST CIRCUITS AND WAVEFORMS L VIN VDS RG G D DUT + VDD tp S IDS Figure 3. Inductive Load Switching Test Circuit V VIN V T av T p V (BR)DSS I pk VDS VDD V DS(on) IDS Figure. Inductive Load Switching Waveforms

11 PACKAGE DIMENSIONS X B Y Z H G A D S C. (.) M Z Y S X S. (.) M SEATING PLANE Y. (.) M SOIC CASE 7 7 ISSUE AK N X M K SOLDERING FOOTPRINT* J..6 NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.7 (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 7 6 ARE OBSOLETE. NEW STANDARD IS 7 7. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.7 BSC. BSC H.... J K M N.... S STYLE : PIN. SOURCE. GATE 3. SOURCE. GATE. DRAIN 6. DRAIN 7. DRAIN. DRAIN SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 9 E. 3nd Pkwy, Aurora, Colorado USA Phone: or 3 36 Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: 3 7 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCVD/D