High Performance Silicon Gate CMOS

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1 igh Performance Silicon Gate MOS The M7400A is identical in pinout to the S00. The device inputs are compatible with Standard MOS outputs; with pullup resistors, they are compatible with STT outputs. Output Drive apability: 0 STT oads Outputs Directly Interface to MOS, NMOS and TT Operating oltage Range: 2 to 6 ow Input urrent: µa igh Noise Immunity haracteristic of MOS Devices In ompliance With the JEDE Standard No. 7A Requirements hip omplexity: 32 FETs or 8 Equivalent Gates A B A2 B2 A3 B3 A4 B OGI DIAGRAM PIN 4 = PIN 7 = GND 3 Y 6 Y2 8 Y3 Y4 Pinout: 4 ead Packages (Top iew) B4 A4 Y4 B3 A3 Y Y = AB PDIP 4 N SUFFIX ASE 646 SOI 4 D SUFFIX ASE 75A TSSOP 4 DT SUFFIX ASE 948G MARKING DIAGRAMS 4 4 M7400AN AWYYWW 4 A = Assembly ocation W or = Wafer ot YY or Y = Year WW or W = Work Week A FUNTION TABE Inputs B Output Y 00A AWYWW 00A AYW A B Y A2 B2 Y2 GND ORDERING INFORMATION Device Package Shipping M7400AN PDIP / Box M7400AD SOI 4 55 / Rail M7400ADR2 SOI / Reel M7400ADT TSSOP 4 96 / Rail M7400ADTR2 TSSOP / Reel Semiconductor omponents Industries,, 2000 March, 2000 Rev. 8 Publication Order Number: M7400A/D

2 M7400A MAXIMUM RATINGS* Symbol Parameter Î alue Unit D Supply oltage (Referenced to GND) Î 0.5 to in D Input oltage (Referenced to GND) Î 0.5 to out D Output oltage (Referenced to GND) Î 0.5 to Iin D Input urrent, per Pin Î ± 20 ma Iout D Output urrent, per Pin Î ± 25 ma I D Supply urrent, and GND Pins Î ± 50 ma PD Power Dissipation in Still Air, Plastic DIP Î 750 mw SOI Package 500 TSSOP Package 450 Î Tstg Storage Temperature 65 to + 50 T ead Temperature, mm from ase for 0 Seconds Î Plastic DIP, SOI or TSSOP Package Î 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating onditions. Derating Plastic DIP: 0 mw/ from 65 to 25 SOI Package: 7 mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 For high frequency or heavy load considerations, see hapter 2 of the ON Semiconductor igh Speed MOS Data Book (D29/D). REOMMENDED OPERATING ONDITIONS Symbol Parameter Min Max Unit D Supply oltage (Referenced to GND) in, out D Input oltage, Output oltage (Referenced to GND) 0 TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time = ns (Figure ) = = This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. 2

3 M7400A D ARATERISTIS (oltages Referenced to GND) Symbol Parameter ondition I I O O Iin I Minimum igh evel Input oltage Maximum ow evel Input oltage Minimum igh evel Output oltage Maximum ow evel Output oltage Maximum Input eakage urrent Maximum Quiescent Supply urrent (per Package) out = or Iout 20µA out = or Iout 20µA in = I or I Iout 20µA in =I or I in = I or I Iout 20µA in = I or I Iout 2.4mA Iout 4.0mA Iout 5.2mA Iout 2.4mA Iout 4.0mA Iout 5.2mA Guaranteed imit 55 to Unit in = or GND ± ±.0 ±.0 µa in = or GND Iout = 0µA µa NOTE: Information on typical parametric values can be found in hapter 2 of the ON Semiconductor igh Speed MOS Data Book (D29/D). A ARATERISTIS ( = 50 pf, Input tr = tf = 6 ns) Symbol tp, tp tt, tt Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures and 2) Maximum Output Transition Time, Any Output (Figures and 2) Guaranteed imit 55 to Unit in Maximum Input apacitance pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see hapter 2 of the ON Semiconductor igh Speed MOS Data Book (D29/D) , = 5.0, EE = 0 PD Power Dissipation apacitance (Per Buffer)* 22 pf * Used to determine the no load dynamic power consumption: PD = PD 2 f + I. For load considerations, see hapter 2 of the ON Semiconductor igh Speed MOS Data Book (D29/D). ns ns 3

4 M7400A tf tr INPUT A OR B 90% 50% 0% GND tp tp OUTPUT Y 90% 50% 0% tt tt Figure. Switching Waveforms TEST POINT DEIE UNDER TEST OUTPUT * *Includes all probe and jig capacitance Figure 2. Test ircuit A B Y Figure 3. Expanded ogic Diagram (/4 of the Device) 4

5 M7400A PAKAGE DIMENSIONS A F G D N B SEATING PANE K PDIP 4 N SUFFIX ASE ISSUE M J NOTES:. EADS WITIN 3 (0.005) RADIUS OF TRUE POSITION AT SEATING PANE AT MAXIMUM MATERIA ONDITION. 2. DIMENSION TO ENTER OF EADS WEN FORMED PARAE. 3. DIMENSION B DOES NOT INUDE MOD FAS. 4. ROUNDED ORNERS OPTIONA. INES MIIMETERS DIM MIN MAX MIN MAX A B D F G 00 BS 2.54 BS J K BS 7.62 BS M N A B P 7 P SOI 4 D SUFFIX ASE 75A 03 ISSUE F 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOERANING PER ANSI YM, ONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 27 (0.005) TOTA IN EXESS OF TE D DIMENSION AT MAXIMUM MATERIA ONDITION. T SEATING PANE G D 4 P K 0.25 (0.00) M T B S A S R X 45 M J F MIIMETERS INES DIM MIN MAX MIN MAX A B D F G.27 BS BS J K M P R

6 M7400A PAKAGE DIMENSIONS TSSOP 4 DT SUFFIX ASE 948G 0 ISSUE O 5 (0.006) T 5 (0.006) T 0 (0.004) T SEATING PANE U U S 2X /2 PIN IDENT. S D 4 4X K REF 0 (0.004) M T U S S N (0.00) M B U 7 A G N J J F DETAI E K K ÇÇ ÉÉ SETION N N DETAI E W NOTES:. DIMENSIONING AND TOERANING PER ANSI YM, ONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INUDE MOD FAS, PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXEED 5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXESS OF TE K DIMENSION AT MAXIMUM MATERIA ONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INES DIM MIN MAX MIN MAX A B D F G 0.65 BS BS J J K K BS BS M

7 M7400A Notes 7

8 M7400A ON Semiconductor and are trademarks of Semiconductor omponents Industries, (SI). SI reserves the right to make changes without further notice to any products herein. SI makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SI assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SI data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SI does not convey any license under its patent rights nor the rights of others. SI products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SI product could create a situation where personal injury or death may occur. Should Buyer purchase or use SI products for any such unintended or unauthorized application, Buyer shall indemnify and hold SI and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SI was negligent regarding the design or manufacture of the part. SI is an Equal Opportunity/Affirmative Action Employer. PUBIATION ORDERING INFORMATION NORT AMERIA iterature Fulfillment: iterature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada ONlit@hibbertco.com Fax Response ine: or Toll Free USA/anada N. American Technical Support: Toll Free USA/anada EUROPE: D for ON Semiconductor European Support German Phone: (+) (M F :00pm to 5:00pm Munich Time) ONlit german@hibbertco.com French Phone: (+) (M F :00pm to 5:00pm Toulouse Time) ONlit french@hibbertco.com English Phone: (+) (M F 2:00pm to 5:00pm UK Time) ONlit@hibbertco.com EUROPEAN TO FREE AESS*: *Available from Germany, France, Italy, England, Ireland ENTRA/SOUT AMERIA: Spanish Phone: (Mon Fri 8:00am to 5:00pm MST) ONlit spanish@hibbertco.com ASIA/PAIFI: D for ON Semiconductor Asia Support Phone: (Tue Fri 9:00am to :00pm, ong Kong Time) Toll Free from ong Kong & Singapore: ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan ustomer Focus enter 4 32 Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r4525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 8 M7400A/D

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