SN74LS42MEL. One of Ten Decoder LOW POWER SCHOTTKY
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1 SN74S42 One of Ten Decoder The STT/ MSI SN74S42 is a Multipurpose Decoder designed to accept four BCD inputs and provide ten mutually exclusive outputs. The S42 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TT families. Multifunction Capability Mutually Exclusive Outputs Demultiplexing Capability Input Clamp Diodes imit igh Speed Termination Effects OW POWER SCOTTKY GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I O Output Current igh 0.4 ma I O Output Current ow 8.0 ma PASTIC N SUFFIX CASE 648 SOIC D SUFFIX CASE 75B SOEIAJ M SUFFIX CASE 966 ORDERING INFORMATION Device Package Shipping SN74S42N Pin DIP 2000 Units/Box SN74S42D SOIC 38 Units/Rail SN74S42DR2 SOIC 2500/Tape & Reel SN74S42M SOEIAJ See Note SN74S42ME SOEIAJ See Note. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, C, 2006 July, 2006 Rev. 8 Publication Order Number: SN74S42/D
2 SN74S42 CONNECTION DIAGRAM DIP (TOP VIEW) V CC A 0 A A 2 A GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. OADING (Note a) PIN NAMES IG OW A 0 A 3 0 to 9 Address Inputs Outputs, Active OW 0.5 U.. 0 U U.. 5 U.. Мa) TT Unit oad (U..) = 40 A IG/.6 ma OW. OGIC SYMBO A 0 A A 2 A V CC = PIN GND = PIN 8 OGIC DIAGRAM A 0 A A 2 A V CC = PIN GND = PIN 8 = PIN NUMBERS 2
3 SN74S42 3 FUNCTIONA DESCRIPTION The S42 decoder accepts four active IG BCD inputs and provides ten mutually exclusive active OW outputs, as shown by logic symbol or diagram. The active OW outputs facilitate addressing other MSI units with OW input enables. The logic design of the S42 ensures that all outputs are IG when binary codes greater than nine are applied to the inputs. The most significant input A 3 produces a useful inhibit function when the S42 is used as a one-of-eight decoder. The A 3 input can also be used as the Data input in an 8-output demultiplexer application. TRUT TABE A 0 A A 2 A = IG Voltage evel = OW Voltage evel
4 SN74S42 DC CARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits Symbol Parameter Min Typ Max Unit V I Input IG Voltage 2.0 V Test Conditions Guaranteed Input IG Voltage for All Inputs V I Input OW Voltage 0.8 V Guaranteed Input OW Voltage for All Inputs V IK Input Clamp Diode Voltage V V CC = MIN, I IN = 8 ma V O Output IG Voltage V V CC = MIN, I O = MAX, V IN = V I or V I per Truth Table V O I I Output OW Voltage Input IG Current V I O = 4.0 ma V CC = V CC MIN, V IN = V I or V I V I O = 8.0 ma per Truth Table 20 μa V CC = MAX, V IN = 2.7 V 0. ma V CC = MAX, V IN = 7.0 V I I Input OW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note 2) ma V CC = MAX I CC Power Supply Current 3 ma V CC = MAX 2. Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (T A = 25 C) Symbol t P t P t P t P Propagation Delay (2 evels) Propagation Delay (3 evels) Parameter imits Min Typ Max Unit ns Figure 2 ns Figure Test Conditions V CC = 5.0 V C = 5 pf AC WAVEFORMS V IN.3 V.3 V V IN.3 V.3 V t P t P t P t P V OUT.3 V.3 V V OUT.3 V.3 V Figure. Figure 2. 4
5 SN74S42 PACKAGE DIMENSIONS N SUFFIX PASTIC PACKAGE CASE ISSUE R A 8 G F 9 D P B S C K 0.25 (0.00) M T SEATING T PANE A M J M. DIMENSIONING AND TOERANCING PER ANSI Y4.5M, CONTROING DIMENSION: INC. 3. DIMENSION TO CENTER OF EADS WEN FORMED PARAE. 4. DIMENSION B DOES NOT INCUDE MOD FAS. 5. ROUNDED CORNERS OPTIONA. INCES MIIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC 2.54 BSC BSC.27 BSC J K M S
6 SN74S42 PACKAGE DIMENSIONS D SUFFIX PASTIC SOIC PACKAGE CASE 75B 05 ISSUE J T SEATING PANE 9 8 G A K B D P 0.25 (0.00) M T B S A S P 8 P 0.25 (0.00) M B S C M R X 45 J F. DIMENSIONING AND TOERANCING PER ANSI Y4.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.27 (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M P R
7 SN74S42 PACKAGE DIMENSIONS M SUFFIX SOEIAJ PACKAGE CASE ISSUE O e 9 Z b D A E A 0.3 (0.005) M 0.0 (0.004) 8 E VIEW P M E Q DETAI P c. DIMENSIONING AND TOERANCING PER ANSI Y4.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D AND E DO NOT INCUDE MOD FAS OR PROTRUSIONS AND ARE MEASURED AT TE PARTING INE. MOD FAS OR PROTRUSIONS SA NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EAD WIDT DIMENSION (b) DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE EAD WIDT DIMENSION AT MAXIMUM MATERIA CONDITION. DAMBAR CANNOT BE OCATED ON TE OWER RADIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT EAD TO BE 0.46 ( 0.08). MIIMETERS INCES DIM MIN MAX MIN MAX A A b c D E e.27 BSC BSC E E M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 53, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative SN74S42/D
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MMBZ5xxBLT Series, SZMMBZ5xxBLTG Series Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed
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More informationMARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10173L AWLYYWW
The MC03 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data
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The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW
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The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes
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More informationMARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place
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