SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY

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1 Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. ata appears on the bus when the Output Enable () is LOW. When is HIGH the bus output is in the high impedance state. The SN74LS374 is a high-speed, low-power Octal -type Flip-Flop featuring separate -type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock () and Output Enable () is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families. Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered -Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp iodes Limit High Speed Termination Effects GUARANTEE OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C LOW POWER SCHOTTKY PIP N SUFFIX CASE 738 SOIC W SUFFIX CASE 75 MARKING IAGRAMS SN74LS37xN AWLYYWW LS37x AWLYYWW I OH Output Current High 2.6 ma I OL Output Current Low 24 ma SIAJ M SUFFIX CASE LS37x AWLYWW x = 3 or 4 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 06 July, 06 Rev. 9 Publication Order Number: SN74LS373/

2 CONNECTION IAGRAM IP (TOP VIEW) SN74LS373 SN74LS374 V CC O O 6 O O 4 LE V CC O O 6 O O O 0 0 O O O 3 GN NOTE: The Flatpak version has the same pinouts (Connection iagram) as the ual In-Line Package O 0 0 O O O 3 GN LOAING (Note a) PIN NAMES HIGH LOW 0 7 LE O 0 O 7 ata Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH Going Edge) Input Output Enable (Active LOW) Input Outputs 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L U.L U.L U.L U.L. 5 U.L. NOTES: Мa) TTL Unit Load (U.L.) = 40 A HIGH/.6 ma LOW. LS373 n LE O n H H L H L H L L X L L 0 X X H Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance TRUTH TABLE LS374 n LE O n H L H L L L X X H Z* * Note: Contents of flip-flops unaffected by the state of the Output Enable input (). 2

3 LOGIC IAGRAMS SN74LS373 LATCH ENABLE LE G G 2 G 3 G 3 4 G 4 5 G G G V CC = PIN GN = PIN 0 = PIN NUMBERS O 0 O O 2 O 3 O 4 O 5 O 6 O SN74LS O 0 O O 2 O 3 O 4 O 5 O 6 O C CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Min Typ Max V IH Input HIGH Voltage 2.0 V V IL Input LOW Voltage 0.8 Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs V IK Input Clamp iode Voltage V V CC = MIN, I IN = 8 ma V OH Output HIGH Voltage V V CC = MIN, I OH = MAX, V IN = V IH or V IL per Truth Table V OL Output LOW Voltage V I OL = 2 ma V CC = V CC MIN, V IN = V IL or V IH V I OL = 24 ma per Truth Table I OZH Output Off Current HIGH μa V CC = MAX, V OUT = 2.7 V I OZL Output Off Current LOW μa V CC = MAX, V OUT = 0.4 V I IH Input HIGH Current μa V CC = MAX, V IN = 2.7 V 0. ma V CC = MAX, V IN = 7.0 V I IL Input LOW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note ) ma V CC = MAX I CC Power Supply Current 40 ma V CC = MAX. Not more than one output should be shorted at a time, nor for more than second. 3

4 AC CHARACTERISTICS (T A = 25 C, V CC = 5.0 V) Symbol Parameter LS373 Limits LS374 Min Typ Max Min Typ Max f MAX Maximum Clock Frequency MHz t PLH t PHL t PLH t PHL Propagation elay, ata to Output Clock or Enable to Output Unit ns ns Test Conditions C L = 45 pf, R L = 667 Ω Output Enable Time ns Output isable Time ns C L = 5.0 pf AC SETUP REUIREMENTS (T A = 25 C, V CC = 5.0 V) Limits LS373 LS374 Symbol Parameter Min Max Min Max Unit t W Clock Pulse Width 5 5 ns t s Setup Time 5.0 ns t h Hold Time 0 ns EFINITION OF TERMS SETUP TIME (t s ) is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. HOL TIME (t h ) is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition. SN74LS373 AC WAVEFORMS t W t W LE.3 V t s t h n t PLH t PHL OUTPUT Figure..3 V.3 V.3 V.3 V V OUT V OH.3 V.3 V V OUT.3 V.3 V V OL 0.5 V 0.5 V Figure 2. Figure 3. 4

5 SN74LS373 AC LOA CIRCUIT V CC R L SWITCH POSITIONS SYMBOL SW SW2 SW Open Open TO OUTPUT UNER TEST 5.0 kω C L * SW2 * Includes Jig and Probe Capacitance. Figure 4. SN74LS374 AC WAVEFORMS t W H t W L.3 V.3 V.3 V.3 V.3 V t s t h n.3 V V OUT.3 V.3 V OUTPUT t PLH t PHL.3 V.3 V Figure V V OL Figure 5..3 V.3 V V OUT.3 V V OH.3 V 0.5 V Figure 7. 5

6 SN74LS374 AC LOA CIRCUIT V CC SWITCH POSITIONS R L SYMBOL SW Open SW2 SW Open TO OUTPUT UNER TEST 5.0 kω C L * SW2 * Includes Jig and Probe Capacitance. Figure 8. EVICE ORERING INFORMATION evice Order Number Package Type Tape and Reel Size SN74LS373N PIP 440 Units/Box SN74LS373W SOIC WIE 38 Units/Rail SN74LS373WR2 SOIC WIE 2500/Tape and Reel SN74LS373M SIAJ See Note 2 SN74LS373MEL SIAJ See Note 2 SN74LS374N PIP 440 Units/Box SN74LS374W SOIC WIE 38 Units/Rail SN74LS374WR2 SOIC WIE 2500/Tape and Reel SN74LS374M SIAJ See Note 2 SN74LS374MEL SIAJ See Note 2 2. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. 6

7 PACKAGE IMENSIONS N SUFFIX PLASTIC PACKAGE CASE ISSUE E T SEATING PLANE G E A F 0 PL N B K C 0.25 (0.00) M T A M L M J PL 0.25 (0.00) M T B M NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: INCH. 3. IMENSION L TO CENTER OF LEA WHEN FORME PARALLEL. 4. IMENSION B S NOT INCLUE MOL FLASH. INCHES MILLIMETERS IM MIN MAX MIN MAX A B C E BSC.27 BSC F G 0.00 BSC 2.54 BSC J K L BSC 7.62 BSC M N SUFFIX PLASTIC SOIC PACKAGE CASE ISSUE F A H 0X 0.25 M B M 0 E h X 45 NOTES:. IMENSIONS ARE IN MILLIMETERS. 2. INTERPRET IMENSIONS AN TOLERANCES PER ASME Y4.5M, IMENSIONS AN E O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 PER SIE. 5. IMENSION B S NOT INCLUE AMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF B IMENSION AT MAXIMUM MATERIAL CONITION. X B 0.25 M T A S 8X e B B S A A T SEATING PLANE C L MILLIMETERS IM MIN MAX A A B C E e.27 BSC H h L

8 PACKAGE IMENSIONS M SUFFIX SIAJ PACKAGE CASE ISSUE O e E H E 0 Z A b A 0.3 (0.005) M 0.0 (0.004) L E M L ETAIL P VIEW P c NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS AN E O NOT INCLUE MOL FLASH OR PROTRUSIONS AN ARE MEASURE AT THE PARTING LINE. MOL FLASH OR PROTRUSIONS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEA WITH IMENSION (b) S NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEA WITH IMENSION AT MAXIMUM MATERIAL CONITION. AMBAR CANNOT BE LOCATE ON THE LOWER RAIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AN AJACENT LEA TO BE 0.46 ( 0.08). MILLIMETERS INCHES IM MIN MAX MIN MAX A A b c E e.27 BSC BSC H E L L E M Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative SN74LS373/