MC74AC377, MC74ACT377. Octal D Flip Flop with Clock Enable

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1 Octal FlipFlop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, -type flip-flops with individual inputs and outputs. The common buffered Clock () input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each input, one setup time before the LOW-to-HIGH clock traition, is traferred to the corresponding flip-flop s output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock traition for predictable operation. Features Ideal for Addressable Register Applicatio Clock Enable for Address and ata Synchronization Applicatio Eight Edge-Triggered Flip-Flops Buffered Common Clock Outputs Source/Sink 24 ma See MC74AC273 for Master Reset ersion See MC74AC373 for Traparent Latch ersion See MC74AC374 for 3-State ersion ACT377 Has TTL Compatible Inputs MSL = for all Surface Mount Chip Complexity: 292 FETs or 73 Gates PbFree Packages are Available PIP N SUFFIX CASE 738 SOICW W SUFFIX CASE 75 TSSOP T SUFFIX CASE 948E CC O O 6 O O SOEIAJ M SUFFIX CASE 967 ORERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 7 of this data sheet CE O 0 0 O O O 3 GN Figure. Pinout: Lead Packages Conductors (Top iew) EICE MARKING INFORMATION See general marking information in the device marking section on page 7 of this data sheet. PIN NAMES PIN 0 7 CE 0 7 FUNCTION ata Inputs Clock Enable (Active LOW) ata Outputs CE O 0 O O 2 O 3 O 4 O 5 O 6 O 7 Clock Pulse Input Figure 2. Logic Semiconductor Components Industries, LLC, 06 ecember, 06 Rev. 9 Publication Order Number: MC74AC377/

2 MOE SELECT-FUNCTION TABLE Operating Mode Inputs Outputs CE n n Load L H H Load 0 L L L Hold (o Nothing) H = HIGH oltage Level L = LOW oltage Level X = Immaterial = LOW-to-HIGH Clock Traition H X No Change X H X No Change CE O 0 O O 2 O 3 O 4 O 5 O 6 O 7 Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays. Figure 3. Logic iagram 2

3 MAXIMUM RATINGS alue Unit CC C Supply oltage (Referenced to GN) 0.5 to +7.0 in C Input oltage (Referenced to GN) 0.5 to CC +0.5 out C Output oltage (Referenced to GN) 0.5 to CC +0.5 I in C Input Current, per Pin ± ma I out C Output Sink/Source Current, per Pin ±50 ma I CC C CC or GN Current per Output Pin ±50 ma T stg Storage Temperature 65 to +50 C JA Thermal Resistance, (JunctiontoAmbient) SOIC TSSOP PIP ES ES Withstand oltage Human Body Model (Note ) Machine Model (Note 2) Charged evice Model (Note 3) > 00 > 0 > 000 I Latchup Latchup Performance CC = ; TA = 25 C (Note 4) > 00 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability.. Tested to EIA/JES22A4A 2. Tested to EIA/JES22A5A 3. Tested to JES22C0A 4. Tested to EIA/JES78 C/W RECOMMENE OPERATING CONITIONS Min Typ Max Unit CC Supply oltage AC 6.0 ACT in, out C Input oltage, Output oltage (Ref. to GN) 0 CC t r, t f Input Rise and Fall Time (Note 5) AC evices except Schmitt Inputs t r, t f Input Rise and Fall Time (Note 6) ACT evices except Schmitt Inputs / T J Junction Temperature (PIP) 40 C T A Operating Ambient Temperature Range C I OH Output Current High 24 ma I OL Output Current Low 24 ma 5. in from 30% to 70% CC ; see individual ata Sheets for devices that differ from the typical input rise and fall times. 6. in from 0.8 to ; see individual ata Sheets for devices that differ from the typical input rise and fall times. / 3

4 74AC C CHARACTERISTICS IH IL OH OL Minimum High Level Input oltage Maximum Low Level Input oltage Minimum High Level Output oltage Maximum Low Level Output oltage CC () T A = +25 C Typ T A = 40 C to +85 C Unit Conditio Guaranteed Limits OUT = 0. or CC 0. OUT = 0. or CC 0. I OUT = 50 A * IN = IL or IH 2 ma I OH 24 ma 24 ma I OUT = 50 A * IN = IL or IH 2 ma I OH 24 ma 24 ma I IN Maximum Input Leakage Current ±0. ±.0 A I = CC, GN I OL Maximum Input Leakage Current I OH I CC Maximum uiescent Supply Current ma ma OL =.65 Max OH = 3.85 Min A IN = CC or GN *All outputs loaded; thresholds on input associated with output under test. Maximum test duration ms, one output loaded at a time. NOTE: I IN and I are guaranteed to be less than or equal to the respective CC. 74AC AC CHARACTERISTICS For Figures and Waveforms, See Figures 4, 5, and 6. f max Maximum Clock Frequency CC * () t PLH Propagation elay to n t PHL Propagation elay to n * oltage Range is ±0.3 ; oltage Range is ± AC AC OPERATING REUIREMENTS t s Setup Time, HIGH or LOW n to t h Hold Time, HIGH or LOW n to t s Setup Time, HIGH or LOW CE to t h Hold Time, HIGH or LOW CE to CC * () t w Pulse Width HIGH or LOW * oltage Range is ±0.3 ; oltage Range is ±0.5. T A = +25 C C L = 50 pf T A = 40 C to +85 C C L = 50 pf Min Typ Max Min Max Typ T A = +25 C C L = 50 pf Guaranteed Minimum T A = 40 C to +85 C Unit MHz Unit 4

5 74ACT C CHARACTERISTICS CC () IH Minimum High Level Input oltage T A = +25 C Typ.5.5 T A = 40 C to +85 C Unit Conditio Guaranteed Limits OUT = 0. or CC 0. IL Maximum Low Level Input oltage OUT = 0. or CC 0. OH Minimum High Level Output oltage I OUT = 50 A * IN = IL or IH 24 ma I OH 24 ma OL Maximum Low Level Output oltage I OUT = 50 A * IN = IL or IH 24 ma I OH 24 ma I IN Maximum Input Leakage Current ±0. ±.0 A I = CC, GN I CCT Additional Max I CC /Input ma I = CC 2. I OL Minimum ynamic Output Current 75 I OH 75 ma OL =.65 Max OH = 3.85 Min I CC Maximum uiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. Maximum test duration ms, one output loaded at a time A IN = CC or GN 74ACT AC CHARACTERISTICS For Figures and Waveforms See Figures 4, 5, and 6. T CC * T A = +25 C C L = 50 pf A = 40 C to +85 C C L = 50 pf Unit () Min Typ Max Min Max f max Maximum Clock Frequency MHz t PLH Propagation elay to n t PHL Propagation elay to n *oltage Range is ± ACT AC OPERATING REUIREMENTS T CC * T A = +25 C C L = 50 pf A = 40 C to +85 C C L = 50 pf Unit () Typ Guaranteed Minimum t s Setup Time, HIGH or LOW n to t h Hold Time, HIGH or LOW n to.0.0 t s Setup Time, HIGH or LOW CE to t h Hold Time, HIGH or LOW CE to.0.0 t w Pulse Width HIGH or LOW 4.0 *oltage Range is ±0.5. CAPACITANCE alue Typ Unit Test Conditio C IN Input Capacitance pf CC = C P Power issipation Capacitance 90 pf CC = 5

6 SWITCHING WAEFORMS CLOCK t r t f CC t w /fmax t PLH t PHL GN CE CLOCK t su t h CC CC GN Figure 4. Figure 5. ATA t su ALI t h CC GN CLOCK CC GN Figure 6. EICE UNER TEST OUTPUT C L * SCOPE TEST POINT *Includes all probe and jig capacitance Figure 7. Test Circuit 6

7 ORERING INFORMATION MC74AC377N MC74AC377NG MC74ACT377N MC74ACT377NG evice Package Shipping PIP PIP (PbFree) PIP PIP (PbFree) 8 Units / Rail MC74AC377W MC74AC377WG MC74AC377WR2 MC74AC377WR2G MC74ACT377W MC74ACT377WG MC74ACT377WR2 MC74ACT377WR2G SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) SOIC SOIC (PbFree) 38 Units / Rail 000 / Tape & Reel 38 Units / Rail 000 / Tape & Reel MC74AC377T MC74AC377TG MC74AC377TR2 MC74AC377TR2G MC74ACT377MEL MC74ACT377MELG TSSOP* TSSOP* TSSOP* TSSOP* SOEIAJ SOEIAJ (PbFree) 75 Units / Rail 2500 / Tape & Reel 00 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR80/. *These packages are inherently PbFree. MARKING IAGRAMS PIP SOICW TSSOP SOEIAJ MC74ACT377N AWLYYWWG ACT377 AWLYYWWG ACT 377 ALYW 74ACT377 AWLYWWG MC74AC377N AWLYYWWG AC377 AWLYYWWG AC 377 ALYW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = PbFree Package (Note: Microdot may be in either location) 7

8 PACKAGE IMENSIONS PIP N SUFFIX PLASTIC IP PACKAGE CASE ISSUE E A 0 B NOTES:. IMENSIONING AN TOLERANCING PER ANSI YM, CONTROLLING IMENSION: INCH. 3. IMENSION L TO CENTER OF LEA WHEN FORME PARALLEL. 4. IMENSION B OES NOT INCLUE MOL FLASH. T SEATING PLANE G E F N K C PL 0.25 (0.00) M T A M L M J PL 0.25 (0.00) M T B M INCHES MILLIMETERS IM MIN MAX MIN MAX A B C E BSC.27 BSC F G 0.00 BSC 2.54 BSC J K L BSC 7.62 BSC M N SOICW W SUFFIX CASE 7505 ISSUE G H 0X 0.25 M B M E A h X 45 NOTES:. IMENSIONS ARE IN MILLIMETERS. 2. INTERPRET IMENSIONS AN TOLERANCES PER ASME YM, IMENSIONS AN E O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 PER SIE. 5. IMENSION B OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF B IMENSION AT MAXIMUM MATERIAL CONITION. X B 0.25 M T A S 8X e 0 B B S A A T SEATING PLANE C L MILLIMETERS IM MIN MAX A A B C E e.27 BSC H h L

9 PACKAGE IMENSIONS TSSOP T SUFFIX CASE 948E02 ISSUE C 0.5 (0.006) T L 0.5 (0.006) T U 2X L/2 PIN IENT U S S C 0.00 (0.004) T SEATING PLANE X K REF 0.0 (0.004) M T U S S 0 A G H B U N J J N K K ÍÍÍÍ ÍÍÍÍ SECTION NN F ETAIL E 0.25 (0.00) ETAIL E M NOTES:. IMENSIONING AN TOLERANCING PER ANSI YM, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC W H J J K K L 6.40 BSC BSC M SOLERING FOOTPRINT* PITCH 6X X.26 IMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. 9

10 PACKAGE IMENSIONS SOEIAJ M SUFFIX CASE 9670 ISSUE A e E H E 0 Z A L E M L ETAIL P IEW P c NOTES: М. IMENSIONING AN TOLERANCING PER ANSI YM, 982. М 2. CONTROLLING IMENSION: MILLIMETER. М 3. IMENSIONS AN E O NOT INCLUE MOL FLASH OR PROTRUSIONS AN ARE MEASURE AT THE PARTING LINE. MOL FLASH OR PROTRUSIONS SHALL NOT EXCEE 0.5 (0.006) PER SIE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. М 5. THE LEA WITH IMENSION (b) OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEA WITH IMENSION AT MAXIMUM MATERIAL CONITION. AMBAR CANNOT BE LOCATE ON THE LOWER RAIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AN AJACENT LEA TO BE 0.46 ( 0.08). b 0.3 (0.005) M A 0.0 (0.004) MILLIMETERS INCHES IM MIN MAX MIN MAX A A b c E e.27 BSC BSC H E L L E M Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74AC377/

11 Mouser Electronics Authorized istributor Click to iew Pricing, Inventory, elivery & Lifecycle Information: ON Semiconductor: MC74AC377T MC74AC377TR2 MC74AC377W MC74AC377WR2 MC74AC377N MC74ACT377W MC74ACT377WR2 MC74ACT377MEL MC74ACT377N MC74ACT377NG

SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY

SN74LS373, SN74LS374. Octal Transparent Latch with 3 State Outputs; Octal D Type Flip Flop with 3 State Output LOW POWER SCHOTTKY Octal Transparent Latch with 3 State Outputs; Octal Type Flip Flop with 3 State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops