MC74HC374A. Octal 3-State Non-Inverting D Flip-Flop. High Performance Silicon Gate CMOS

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1 M7H37A Octal 3-State Non-Inverting Flip-Flop High Performance Silicon Gate MOS The M7H37A is identical in pinout to the LS37. The device inputs are compatible with standard MOS outputs; with pullup resistors, they are compatible with LSTTL outputs. ata meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip flops, but when Output Enable is high, the outputs are forced to the high impedance state; thus, data may be stored even when the outputs are not enabled. The H37A is identical in function to the H7A which has the input pi on the opposite side of the package from the output. This device is similar in function to the H3A which has inverting outputs. Features Output rive apability: LSTTL Loads Outputs irectly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent:.0 A High Noise Immunity haracteristic of MOS evices In ompliance with the Requirements efined by JEE Standard No. 7 A hip omplexity: FETs or. Equivalent Gates NL Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE 00 ualified and PPAP apable These evices are Pb Free and are RoHS ompliant ATA INPUTS LOK LOGI IAGRAM NONINERTING S SOI W SUFFIX ASE 7 MARKING IAGRAMS 7H37A AWLYYWWG SOI PIN ASSIGNMENT ENABLE GN H 37A ALYW TSSOP A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNTION TABLE TSSOP T SUFFIX ASE 98E 7 7 LOK Inputs Output Output Enable lock L H H L L L L L,H, X No hange H X X Z ENABLE PIN = PIN 0 = GN X = don t care Z = high impedance ORERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page of this data sheet. Semiconductor omponents Industries, LL, August, Rev. Publication Order Number: M7H37A/

2 M7H37A MAXIMUM RATINGS Symbol Parameter alue Supply oltage (Referenced to GN) 0. to +7.0 in Input oltage (Referenced to GN) 0. to + 0. out Output oltage (Referenced to GN) 0. to + 0. I in Input urrent, per Pin ± ma I out Output urrent, per Pin ±3 ma I Supply urrent, and GN Pi ±7 ma P Power issipation in Still Air, SOI Package TSSOP Package 0 T stg Storage Temperature to +0 T L Lead Temperature, mm from ase for 0 Seconds (SOI, SSOP or TSSOP Package) 0 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. erating: SOI Package: 7 mw/ from to TSSOP Package:. mw/ from to mw This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GN ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. REOMMENE OPERATING ONITIONS Symbol Parameter Min Max Supply oltage (Referenced to GN) in, out Input oltage, Output oltage (Referenced to GN) 0 T A Operating Temperature, All Package Types + t r, t f Input Rise and Fall Time = (Figure ) = = Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELETRIAL HARATERISTIS (oltages Referenced to GN) Symbol Parameter Test onditio IH Minimum High Level Input oltage out = 0. or 0. I out A IL Maximum Low Level Input oltage out = 0. or 0. I out A OH OL Minimum High Level Output oltage Maximum Low Level Output oltage in = IH or IL I out A in = IH or IL in = IH or IL I out A in = IH or IL I out. ma I out ma I out 7.8 ma I out. ma I out ma I out 7.8 ma to I in Maximum Input Leakage urrent in = or GN ±0. ±.0 ±.0 A

3 M7H37A ELETRIAL HARATERISTIS (oltages Referenced to GN) (continued) Symbol I OZ I Parameter Maximum Three State Leakage urrent Maximum uiescent Supply urrent (per Package) Test onditio Output in High Impedance State in = IL or IH out = or GN in = or GN I out = 0 A to 8 ±0. ± ±0 A 0 0 A A ELETRIAL HARATERISTIS ( L = 0 pf, Input t r = t f = ) Symbol Parameter f max Maximum lock Frequency ( uty ycle) t PLH t PHL t PLZ t PHZ t PZL t PZH t TLH t THL Maximum Propagation elay, Input lock to (Figures and ) Maximum Propagation elay, Output Enable to (Figures 3 and ) Maximum Propagation elay, Output Enable to (Figures 3 and ) Maximum Output Traition Time, Any Output (Figures and ) to 8 in Maximum Input apacitance pf out Maximum Three State Output apacitance (Output in High Impedance State) MHz pf = P Power issipation apacitance (Per Enabled Output)* * Used to determine the no load dynamic power coumption: P = P f + I. 3 pf 3

4 M7H37A TIMING REUIREMENTS ( L = 0 pf, Input t r = t f = ) Symbol Parameter Figure olts t su Minimum Setup Time, ata to lock 3 t h Minimum Hold Time, lock to ata 3 t w Minimum Pulse Width, lock t r, t f Maximum Input Rise and Fall Times to 8 Min Max Min Max Min Max SWITHING WAEFORMS LOK 90% 0% 90% 0% t r t f t W t PLH t TLH /f max t PHL t THL GN ENABLE t PZH t PHZ t PZL t PLZ 0% 90% GN HIGH IMPEANE OL OH HIGH IMPEANE Figure. Figure. ALI ATA GN t su t h LOK GN Figure 3.

5 M7H37A TEST IRUITS TEST POINT TEST POINT EIE UNER TEST L * EIE UNER TEST k L * ONNET TO WHEN TESTING t PLZ AN t PZL. ONNET TO GN WHEN TESTING t PHZ AN t PZH. *Includes all probe and jig capacitance Figure. *Includes all probe and jig capacitance Figure lock Output Enable Figure. Expanded Logic iagram ORERING INFORMATION M7H37AWG evice Package Shipping SOI WIE s / Rail NL7H37AWG* M7H37AWRG NL7H37AWRG* M7H37ATG M7H37ATRG SOI WIE SOI WIE SOI WIE TSSOP TSSOP s / Rail 000 Tape & Reel 000 Tape & Reel 7 s / Rail Tape & Reel NL7H37ATRG* TSSOP Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR80/. *NL Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE 00 ualified and PPAP apable.

6 M7H37A PAKAGE IMENSIONS TSSOP T SUFFIX ASE 98E 0 ISSUE 0. (0.00) T L 0. (0.00) T U X L/ PIN IENT U S S 0 (0.00) T SEATING PLANE X K REF (0.00) M T U S S 0 A G H B U N J J N K K ÍÍÍÍ ÍÍÍÍ SOLERING FOOTPRINT* 7.0 SETION N N 0. (0.00) M NOTES:. IMENSIONING AN TOLERANING PER ANSI YM, 98.. ONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXEE 0. (0.00) PER SIE.. IMENSION B OES NOT INLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXEE 0. (0.00) PER SIE.. IMENSION K OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K IMENSION AT MAXIMUM MATERIAL ONITION.. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. F MILLIMETERS INHES IM MIN MAX MIN MAX ETAIL E A B W F G 0. BS 0.0 BS H J ETAIL E J K K L.0 BS 0. BS M PITH X 0.3 X. IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/.

7 M7H37A PAKAGE IMENSIONS SOI W SUFFIX ASE 7 0 ISSUE G H 0X 0. M B M E A h X NOTES:. IMENSIONS ARE IN MILLIMETERS.. INTERPRET IMENSIONS AN TOLERANES PER ASME YM, IMENSIONS AN E O NOT INLUE MOL PROTRUSION.. MAXIMUM MOL PROTRUSION 0. PER SIE.. IMENSION B OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXESS OF B IMENSION AT MAXIMUM MATERIAL ONITION. X B 0. M T A S 8X e 0 B B S A A T SEATING PLANE L MILLIMETERS IM MIN MAX A.3. A 0. B E e.7 BS H h L ON Semiconductor and the are registered trademarks of Semiconductor omponents Industries, LL (SILL) or its subsidiaries in the ed States and/or other countries. SILL ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at Marking.pdf. SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution enter for ON Semiconductor P.O. Box 3, enver, olorado 807 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@oemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative M7H37A/