MC74HC4040A. 12 Stage Binary Ripple Counter. High Performance Silicon Gate CMOS

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1 M74HA 2 Stage Binary Ripple ounter High Performance Silicon Gate MOS The M74A is identical in pinout to the standard MOS M. The device inputs are compatible with standard MOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device coists of 2 master slave flip flops. The output of each flip flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative going edge of the lock input. Reset is asynchronous and active high. State changes of the outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the lock of the HA for some desig. Features Output Drive apability: 0 LSTTL Loads Outputs Directly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent: A High Noise Immunity haracteristic of MOS Devices In ompliance With JEDE Standard No. 7A Requirements hip omplexity: 38 FETs or.5 Equivalent Gates Pb Free Packages are Available* PDIP 6 N SUFFIX ASE 648 SOI 6 D SUFFIX ASE 75B TSSOP 6 DT SUFFIX ASE 48F SOEIAJ 6 F SUFFIX ASE 66 6 MARKING DIAGRAMS M74HAN AWLYYWWG 6 6 HAG AWLYWW 6 H A ALYW 74HA ALYWG A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb Free Package = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor omponents Industries, LL, 2005 June, 2005 Rev. 5 Publication Order Number: M74HA/D

2 M74HA lock Reset Pin 6 = Pin 8 = GND 2 FUNTION TABLE lock Reset Output State X L L H No harge Advance to Next State All Outputs Are Low 0 8 Reset lock GND 8 Figure. Logic Diagram Figure 2. Pinout: 6 Lead Plastic Package (Top iew) ORDERING INFORMATION Device Package Shipping M74HAN PDIP Units / Box M74HANG PDIP 6 (Pb Free) 2000 Units / Box M74HAD SOI 6 48 Units / Rail M74HADG SOI 6 (Pb Free) 48 Units / Rail M74HADR2 SOI Units / Reel M74HADR2G SOI 6 (Pb Free) 2500 Units / Reel M74HADTR2 TSSOP 6* 2500 Units / Reel M74HADTR2G TSSOP 6* 2500 Units / Reel M74HAF SOEIAJ 6 50 Units / Rail M74HAFG SOEIAJ 6 (Pb Free) 50 Units / Rail M74HAFEL SOEIAJ Units / Reel M74HAFELG SOEIAJ 6 (Pb Free) 2000 Units / Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 M74HA MAXIMUM RATINGS SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎ alue ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D Supply oltage (Referenced to GND) ÎÎÎÎÎ 0.5 to + 7.0ÎÎÎ ÎÎÎÎ in ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D Input oltage (Referenced to GND) ÎÎÎÎÎ 0.5 to + 0.5ÎÎÎ ÎÎÎÎ out ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D Output oltage (Referenced to GND) ÎÎÎÎÎ 0.5 to + 0.5ÎÎÎ ÎÎÎÎ I in ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D Input urrent, per Pin ÎÎÎÎÎ ± 20 ÎÎÎ ma ÎÎÎÎ I out ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D Output urrent, per Pin ÎÎÎÎÎ ± 25 ÎÎÎ ma ÎÎÎÎ I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D Supply urrent, and GND Pi ÎÎÎÎÎ ± 50 ÎÎÎ ma ÎÎÎÎ P D ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, Plastic DIP ÎÎÎÎÎ 750 ÎÎÎ mw SOI Package 500 TSSOP Package 450 ÎÎÎÎ T stg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Storage Temperature Range 65 to + 50 ÎÎÎÎ T L ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, mm from ase for 0 Seconds ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Plastic DIP, SOI or TSSOP Package ÎÎÎÎÎ 260 ÎÎÎ Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditio) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating Plastic DIP: 0 mw/ from 65 to 25 SOI Package: 7 mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 For high frequency or heavy load coideratio, see hapter 2 of the ON Semiconductor High Speed MOS Data Book (DL2/D). REOMMENDED OPERATING ONDITIONS Symbol Parameter Min Max Unit D Supply oltage (Referenced to GND) in, out D Input oltage, Output oltage (Referenced to GND) 0 T A Operating Temperature Range, All Package Types t ÎÎÎÎ r, t f Input Rise and Fall Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ = (Figure ) = ÎÎÎ 0 ÎÎÎ 600ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ = ÎÎÎ 0 ÎÎÎ 500ÎÎÎ = 0 0 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. D HARATERISTIS (oltages Referenced to GND) Symbol Parameter ondition Guaranteed Limit 55 to Unit IH Minimum High Level Input oltage out = 0. or 0. I out 20 A IL Maximum Low Level Input oltage out = 0. or 0. I out 20 A OH Minimum High Level Output oltage in = IH or IL I out 20 A in = IH or IL I out 2.4mA I out 4.0mA I out 5.2mA OL Maximum Low Level Output oltage in = IH or IL I out 20 A

4 M74HA D HARATERISTIS (oltages Referenced to GND) Symbol Parameter in = IH or IL ondition I out 2.4mA I out 4.0mA I out 5.2mA 55 to Guaranteed Limit I in Maximum Input Leakage urrent in = or GND ±0. ±.0 ±.0 A I Maximum uiescent Supply urrent (per Package) in = or GND I out = 0 A Unit 4 60 A NOTE: Information on typical parametric values can be found in hapter 2 of the ON Semiconductor High Speed MOS Data Book (DL2/D). A HARATERISTIS ( L = 50 pf, Input t r = t f = 6 ) Symbol f max Parameter Maximum lock Frequency ( Duty ycle) (Figures and 4) t PLH, Maximum Propagation Delay, lock to * t PHL (Figures and 4) t PHL t PLH, t PHL t TLH, t THL Maximum Propagation Delay, Reset to Any (Figures 2 and 4) Maximum Propagation Delay, n to n+ (Figures 3 and 4) Maximum Output Traition Time, Any Output (Figures and 4) Guaranteed Limit 55 to in Maximum Input apacitance pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see hapter 2 of the ON Semiconductor High Speed MOS Data Book (DL2/D). * For T A = 25 and L = 50 pf, typical propagation delay from lock to other outputs may be calculated with the following equatio: = : t P = [ (n )] = : t P = [ (n )] = : t P = [ (n )] = : t P = [ (n )] , = 5.0 PD Power Dissipation apacitance (Per Package)* 3 pf * Used to determine the no load dynamic power coumption: P D = PD 2 f + I. For load coideratio, see hapter 2 of the ON Semiconductor High Speed MOS Data Book (DL2/D). Unit MHz 4

5 M74HA TIMING REUIREMENTS (Input t r = t f = 6 ) Symbol t rec t w t w t r, t f Parameter Minimum Recovery Time, Reset Inactive to lock (Figure 2) Minimum Pulse Width, lock (Figure ) Minimum Pulse Width, Reset (Figure 2) Maximum Input Rise and Fall Times (Figure ) Guaranteed Limit 55 to NOTE: Information on typical parametric values can be found in hapter 2 of the ON Semiconductor High Speed MOS Data Book (DL2/D) Unit PIN DESRIPTIONS INPUTS lock (Pin 0) Negative edge triggering clock input. A high to low traition on this input advances the state of the counter. OUTPUTS thru 2 (Pi, 7, 6, 5, 3, 2, 4, 3, 2, 4, 5, ) Active high outputs. Each n output divides the lock input frequency by 2 N. Reset (Pin ) Active high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all outputs low. SWITHING WAEFORMS lock 0% 0% t f 0% 0% t w t PLH t TLH /f MAX t r t PHL t THL GND lock t rec t w Reset t PHL Any GND GND Figure 3. Figure 4. 5

6 M74HA SWITHING WAEFORMS (continued) TEST POINT n t PLH t PHL GND DEIE UNDER TEST OUTPUT L * n+ *Includes all probe and jig capacitance Figure 5. Figure 6. Test ircuit lock 0 R R Reset 4 = Pin 5 5 = Pin 3 6 = Pin 2 7 = Pin 4 8 = Pin 3 = Pin 2 = Pin 6 GND = Pin 8 Figure 7. Expanded Logic Diagram 6

7 M74HA lock Reset Figure 8. Timing Diagram APPLIATIONS INFORMATION Time Base Generator A 60Hz sinewave obtained through a 00 K resistor connected to a 20 ac power line through a step down traformer is applied to the input of the M54/74H4A, Schmitt-trigger inverter. The H4A squares up the input waveform and feeds the HA. Selecting outputs 5, 0,, and 2 causes a reset every 3600 clocks. The H20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. The resulting output frequency is.0 pulse/minute. 20ac 60Hz NOTE:.0M 20pF Ground MUST be isolated by a traformer or opto isolator for safety reaso. HA lock /2 H /2 H Pulse/Minute Output Figure. Time Base Generator 7

8 M74HA PAKAGE DIMENSIONS PDIP 6 N SUFFIX ASE ISSUE T 6 A 8 B NOTES:. DIMENSIONING AND TOLERANING PER ANSI YM, ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MOLD FLASH. 5. ROUNDED ORNERS OPTIONAL. H G F D 6 PL S K 0.25 (0.00) M T T SEATING PLANE A M J L M INHES MILLIMETERS DIM MIN MAX MIN MAX A B D F G 0.00 BS 2.54 BS H BS.27 BS J K L M S SOI 6 D SUFFIX ASE 75B 05 ISSUE J A 6 8 B P 8 PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANING PER ANSI YM, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. T SEATING PLANE G K D 6 PL 0.25 (0.00) M T B S A S M R X 45 J F MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G.27 BS BS J K M P R

9 M74HA PAKAGE DIMENSIONS TSSOP 6 DT SUFFIX ASE 48F 0 ISSUE A 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 6X K REF 0.0 (0.004) M T U S S 6 8 A G B U N H J N J F DETAIL E DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SETION N N 0.25 (0.00) M W NOTES:. DIMENSIONING AND TOLERANING PER ANSI YM, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K DIMENSION AT MAXIMUM MATERIAL ONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G 0.65 BS BS H J J K K L 6. BS BS M

10 M74HA PAKAGE DIMENSIONS SOEIAJ 6 F SUFFIX ASE 66 0 ISSUE O e 6 Z b D A H E A 0.3 (0.005) M 0.0 (0.004) 8 E IEW P M L E L DETAIL P c NOTES: М. DIMENSIONING AND TOLERANING PER ANSI YM, 82. М 2. ONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXEED 0.5 (0.006) PER SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL ONDITION. DAMBAR ANNOT BE LOATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPAE BETWEEN PROTRUSIONS AND ADJAENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INHES DIM MIN MAX MIN MAX A A b c D E e.27 BS BS H E L L E M Z ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@oemi.com N. American Technical Support: Toll Free USA/anada Japan: ON Semiconductor, Japan ustomer Focus enter 2 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. M74HA/D