MC74HC4020A. 14-Stage Binary Ripple Counter. High Performance Silicon Gate CMOS

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1 M74H20A 4-Stage Binary Ripple ounter High Performance Silicon Gate MOS The M7420A is identical in pinout to the standard MOS M20B. The device inputs are compatible with standard MOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device coists of 4 master slave flip flops with 2 stages brought out to pi. The output of each flip flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active high. State changes of the outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the lock of the H20A for some desig. Features Output Drive apability: 0 LSTTL Loads Outputs Directly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent: A High Noise Immunity haracteristic of MOS Devices In ompliance With JEDE Standard No. 7A Requirements hip omplexity: 398 FETs or 99. Equivalent Gates NL Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE 00 ualified and PPAP apable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS ompliant lock Reset 0 Figure. Logic Diagram Pin 6 = Pin 8 = GND 6 SOI 6 D SUFFIX ASE 7B TSSOP 6 DT SUFFIX ASE 948F MARKING DIAGRAMS H20AG AWLYWW SOI 6 PIN ASSIGNMENT Reset lock GND 6 Lead Package (Top iew) H 20A ALYW ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 6 of this data sheet. 6 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNTION TABLE TSSOP 6 lock Reset Output State X L L H No hange Advance to Next State All Outputs Are Low 8 Semiconductor omponents Industries, LL, 204 August, 204 Rev. 8 Publication Order Number: M74H20A/D

2 M74H20A MAXIMUM RATINGS Symbol Parameter alue Unit D Supply oltage (Referenced to GND) 0. to +7.0 in D Input oltage (Referenced to GND) 0. to + 0. out D Output oltage (Referenced to GND) 0. to + 0. I in D Input urrent, per Pin ±20 ma I out D Output urrent, per Pin ±2 ma I D Supply urrent, and GND Pi ± ma P D Power Dissipation in Still Air SOI Package TSSOP Package 0 4 mw T stg Storage Temperature Range 6 to + T L Lead Temperature, mm from ase for 0 Seconds SOI or TSSOP Package 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating: SOI Package: 7 mw/ from 6 to 2 TSSOP Package: 6. mw/ from 6 to 2 REOMMENDED OPERATING ONDITIONS Symbol Parameter Min Max Unit D Supply oltage (Referenced to GND) in, out D Input oltage, Output oltage (Referenced to GND) 0 T A Operating Temperature Range, All Package Types +2 t r, t f Input Rise/Fall Time = (Figure 2) = = = Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. D HARATERISTIS (oltages Referenced to GND) Symbol Parameter ondition IH Minimum High Level Input oltage out = or I out 20 A IL Maximum Low Level Input oltage out = or I out 20 A OH Minimum High Level Output oltage in = IH or IL I out 20 A in = IH or IL OL Maximum Low Level Output oltage in = IH or IL I out 20 A in = IH or IL I out 2.4mA I out 4.0mA I out.2ma I out 2.4mA I out 4.0mA I out.2ma Guaranteed Limit to I in Maximum Input Leakage urrent in = or GND ± ±.0 ±.0 A I Maximum uiescent Supply urrent (per Package) in = or GND I out = 0 A This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open Unit 4 60 A 2

3 M74H20A A HARATERISTIS ( L = pf, Input t r = t f = 6 ) Symbol f max Parameter Maximum lock Frequency (% Duty ycle) (Figures 2 and ) t PLH, Maximum Propagation Delay, lock to * (Figures 4 and ) t PLH, t TLH, t THL Maximum Propagation Delay, Reset to Any (Figures 3 and ) Maximum Propagation Delay, n to n+ (Figures 4 and ) Maximum Output Traition Time, Any Output (Figures 2 and ) Guaranteed Limit to in Maximum Input apacitance pf * For T A = 2 and L = pf, typical propagation delay from lock to other outputs may be calculated with the following equatio: = : t P = [ (n )] = : t P = [ (n )] = : t P = [ (n )] = : t P = [ (n )] , =.0 Unit MHz PD Power Dissipation apacitance (Per Package)* 38 pf TIMING REUIREMENTS (Input t r = t f = 6 ) Symbol Parameter Guaranteed Limit to Unit t rec Minimum Recovery Time, Reset Inactive to lock (Figure 3) t w Minimum Pulse Width, lock (Figure 2) t w Minimum Pulse Width, Reset (Figure 3) t r, t f Maximum Input Rise and Fall Times (Figure 2)

4 M74H20A PIN DESRIPTIONS INPUTS lock (Pin 0) Negative edge triggering clock input. A high to low traition on this input advances the state of the counter. OUTPUTS, 4 4 (Pi 9, 7,, 4, 6, 3, 2, 4,,, 2, 3) Active high outputs. Each n output divides the lock input frequency by 2 N. Reset (Pin ) Active high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all outputs low. SWITHING WAEFORMS lock 90% % 0% t f 90% % 0% t w t PLH t TLH /f MAX t r t THL GND lock % t rec t w Reset % Any % GND GND Figure 2. Figure 3. TEST POINT n % t PLH GND DEIE UNDER TEST OUTPUT L * n+ % *Includes all probe and jig capacitance Figure 4. Figure. Test ircuit 4

5 M74H20A lock 0 R R Reset 6 = Pin 4 7 = Pin 6 8 = Pin 3 9 = Pin 2 0 = Pin 4 = Pin = Pin 6 GND = Pin 8 Figure 6. Expanded Logic Diagram lock Reset Figure 7. Timing Diagram

6 M74H20A APPLIATIONS INFORMATION Time Base Generator A 60Hz sinewave obtained through a.0 Megohm resistor connected directly to a standard 20 ac power line is applied to the input of the M4/74H4A, Schmitt-trigger inverter. The H4A squares up the input waveform and feeds the H20A. Selecting outputs, 0,, and 2 causes a reset every 3600 clocks. The H20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. The resulting output frequency is.0 pulse/minute. 20ac 60Hz NOTE:.0M 20pF Ground MUST be isolated by a traformer or opto isolator for safety reaso. /6 of H4A H20A lock /2 H /2 H Pulse/Minute Output Figure 8. Time Base Generator ORDERING INFORMATION M74H20ADG Device Package Shipping SOI 6 (Pb Free) 48 Units / Rail M74H20ADR2G M74H20ADTR2G SOI 6 (Pb Free) TSSOP 6 (Pb Free) 20 / Tape & Reel 20 / Tape & Reel NL74H20ADTR2G* TSSOP 6 (Pb Free) 20 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *NL Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE 00 ualified and PPAP apable. 6

7 M74H20A PAKAGE DIMENSIONS TSSOP 6 ASE 948F ISSUE B (0.006) T (0.006) T 0 (0.004) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 6X K REF 0 (0.004) M T U S S K K A G J ÇÇÇ ÉÉÉ B SETION N N U J N 0.2 (0.00) M N F DETAIL E H DETAIL E W NOTES:. DIMENSIONING AND TOLERANING PER ANSI YM, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXEED (0.006) PER SIDE. 4. DIMENSION B DOES NOT INLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXEED 0.2 (0.00) PER SIDE.. DIMENSION K DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K DIMENSION AT MAXIMUM MATERIAL ONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G 0.6 BS BS H J J K K L 6. BS 0.22 BS M SOLDERING FOOTPRINT* PITH 6X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 M74H20A PAKAGE DIMENSIONS A B SOI 6 ASE 7B 0 ISSUE K P 8 PL 0.2 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANING PER ANSI YM, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION (0.006) PER SIDE.. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 27 (0.00) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G.27 BS 0.0 BS J K M P R T SEATING PLANE G D 6 PL 0.2 (0.00) M T B S A S K M R X 4 J F SOLDERING FOOTPRINT* 8X 6. 6X.2 6 6X PITH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor omponents Industries, LL (SILL) or its subsidiaries in the United States and/or other countries. SILL ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at Marking.pdf. SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 63, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@oemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative M74H20A/D