MC14024B. 7-Stage Ripple Counter

Transcription

1 M4024B 7-Stage ipple ounter The M4024B is a 7stage ripple counter with short propagation delays and high maximum clock rates. The eset input has standard noise immunity, however the lock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered. Features Diode Protection on All Inputs Output Traitio Occur on the Falling Edge of the lock Pulse Supply Voltage ange = to 8 apable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the ated Temperature ange PinforPin eplacement for D4024B NLV Prefix for Automotive and Other Applicatio equiring Unique Site and ontrol hange equirements; AE0 ualified and PPAP apable This Device is PbFree and is ohs ompliant MAXIMUM ATINGS (Voltages eferenced to ) Symbol Parameter Value Unit D Supply Voltage ange 0.5 to +8.0 V V in, V out Input or Output Voltage ange (D or Traient) 0.5 to V I in, I out P D Input or Output urrent (D or Traient) per Pin Power Dissipation, per Package (Note ) ± ma 500 mw T A Ambient Temperature ange 55 to +25 T stg Storage Temperature ange 65 to +0 T L Lead Temperature (8Second Soldering) 260 Stresses exceeding those listed in the Maximum atings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Temperature Derating: D/DW Packages: 7.0 mw/ From 65 To 25 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. LOK ESET 7 6 SOI4 D SUFFIX ASE 75A MAKING DIAGAM 4 A WL, L YY, Y WW, W G PIN ASSIGNMENT BG AWLYWW = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package ODEING INFOMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet N 2 N 3 N = PIN 4 = PIN 7 N = NO ONNETION Semiconductor omponents Industries, LL, 204 August, 204 ev. Publication Order Number: M4024B/D

2 M4024B TUTH TABLE lock eset State 0 0 No hange 0 All Outputs Low 0 No hange All Outputs Low 0 No hange All Outputs Low 0 Advance One ount All Outputs Low LOGI DIAGAM LOK 2 ESET = PIN 9 4 = PIN 6 5 = PIN 5 ODEING INFOMATION M4024BDG NLV4024BDG* M4024BD2G Device Package Shipping SOI4 (PbFree) SOI4 (PbFree) SOI4 (PbFree) 55 Units / ail 55 Units / ail 2500 / Tape & eel NLV4024BD2G* SOI4 (PbFree) 2500 / Tape & eel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specificatio Brochure, BD80/D. *NLV Prefix for Automotive and Other Applicatio equiring Unique Site and ontrol hange equirements; AE0 ualified and PPAP apable. 2

3 M4024B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELETIAL HAATEISTIS (Voltages eferenced to ) haracteristic Output Voltage V in = or 0 V in = 0 or Input Voltage (V O = 4.5 or 0.5 ) (V O = 9.0 or.0 ) (V O = 3.5 or.5 ) 0 Level Level 0 Level (V O = 0.5 or 4.5 ) Level (V O =.0 or 9.0 ) (V O =.5 or 3.5 ) Output Drive urrent (V OH = 2.5 ) Source (V OH = 4.6 ) (V OH = 9.5 ) (V OH = 3.5 ) (V OL = 0.4 ) Sink (V OL = 0.5 ) (V OL =.5 ) Symbol V OL V OH V IL V IH I OH I OL Min Max Min Typ (Note 2) Max Min Max Input urrent I in ±0. ± ±0. ±.0 Adc Input apacitance (V in = 0) uiescent urrent (Per Package) Total Supply urrent (Notes 3 & 4) (Dynamic plus uiescent, Per Package) ( L = 50 pf on all outputs, all buffers switching) in 7.5 pf I DD I T I T = (0.3 A/kHz) f + I DD I T = (0.60 A/kHz) f + I DD I T = (.89 A/kHz) f + I DD Product parametric performance is indicated in the Electrical haracteristics for the listed test conditio, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditio. 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. 3. The formulas given are for the typical characteristics only at To calculate total supply current at loads other than 50 pf: I T ( L ) = I T (50 pf) + ( L 50) Vfk where: I T is in A (per package), L in pf, V = ( ) in volts, f in khz is input frequency, and k = Unit madc madc Adc Adc 3

4 M4024B SWITHING HAATEISTIS (Note 5) ( L = 50 pf, T A = 25 ) haracteristic Symbol Min Output ise and Fall Time t TLH, t THL = (.5 /pf) L + 25 t TLH, t THL = (0.75 /pf) L t TLH, t THL = (0.55 /pf) L t TLH, t THL Typ (Note 6) Max Unit Propagation Delay Time lock to t PLH, t PHL = (.7 /pf) L t PLH, t PHL = (0.66 /pf) L + 7 t PLH, t PHL = (0.5 /pf) L + 85 lock to 7 t PLH, t PHL = (.7 /pf) L + 9 t PLH, t PHL = (0.66 /pf) L t PLH, t PHL = (0.5 /pf) L eset to n t PLH, t PHL = (.7 /pf) L + 4 t PLH, t PHL = (0.66 /pf) L + 27 t PLH, t PHL = (0.5 /pf) L + 5 t PLH, t PHL lock Pulse Width t WH eset Pulse Width t WH eset emoval Time t rem lock Input ise and Fall Time t TLH, t THL Input Pulse Frequency f cl 5. The formulas given are for the typical characteristics only at Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance s ms s MHz 4

5 M4024B V OL = V out n OUNT n TO A LOGI " LEVEL. I OH EXTENAL POWE SUPPLY Figure. Typical Output Source haracteristics Test ircuit V OH = V out n I OL EXTENAL POWE SUPPLY Figure 2. Typical Output Sink haracteristics Test ircuit 500 F I D 0.0 F EAMI PULSE GENEATO f L L L L L L L Figure 3. Power Dissipation Test ircuit 5

6 M4024B LOK () ESET (2) (2) 2 () 3 (9) 4 (6) 5 (5) 6 (4) 7 (3) twl twh trem tplh 90% % tplh2 tphl tphl2 90% % tplh3 tphl3 tphl4 tplh4 tplh5 tphl5 tphl6 tplh6 90% % tplh7 tphl7 Input t TLH and t THL = 20 t t2 t3 t4 t5 t6 t7 VDD VSS V OL V OL V OH Figure 4. Functional Waveforms 6

7 M4024B PAKAGE DIMENSIONS H M B M e D 7 3X b A B E 0.25 M A S B S A A SEATING PLANE SOI4 NB ASE 75A03 ISSUE K DETAIL A h X 45 M L A3 DETAIL A NOTES:. DIMENSIONING AND TOLEANING PE ASME Y4.5M, ONTOLLING DIMENSION: MILLIMETES. 3. DIMENSION b DOES NOT INLUDE DAMBA POTUSION. ALLOWABLE POTUSION SHALL BE 0.3 TOTAL IN EXESS OF AT MAXIMUM MATEIAL ONDITION. 4. DIMENSIONS D AND E DO NOT INLUDE MOLD POTUSIONS. 5. MAXIMUM MOLD POTUSION 0. PE SIDE. MILLIMETES INHES DIM MIN MAX MIN MAX A A A b D E e.27 BS 0 BS H h L M SOLDEING FOOTPINT* X.8.27 PITH 4X 0.58 DIMENSIONS: MILLIMETES *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. ON Semiconductor and the are registered trademarks of Semiconductor omponents Industries, LL (SILL) or its subsidiaries in the United States and/or other countries. SILL ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ODEING INFOMATION LITEATUE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@oemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales epresentative M4024B/D