74HC Bit Serial Input/Serial or Parallel Output Shift Register with Latched 3 State Outputs. High Performance Silicon Gate CMOS

Transcription

1 8 Bit Serial Input/Serial or Parallel Output Shift egister with Latched 3 State Outputs High Performance Silicon Gate CMOS The coists of an 8 bit shift register and an 8 bit D type latch with three state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8 bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595 directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. Features Output Drive Capability: 5 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage ange: to V Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the equirements Defined by JEDEC Standard No. 7A ESD Performance: HBM 2000 V; Machine Model 200 V Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595 Improved Propagation Delays % Lower Quiescent Power Improved Input Noise and Latchup Immunity These are Pb Free Devices 6 6 SOIC 6 D SUFFIX CASE B TSSOP 6 DT SUFFIX CASE 948F MAKING DIAGAMS HC595 = Device Code A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ODEING INFOMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. 6 HC595G AWLYWW 6 HC 595 ALYW Semiconductor Components Industries, LLC, 2007 March, 2007 ev. Publication Order Number: /D

2 PIN ASSIGNMENT Q B 6 Q C 2 5 Q A Q D 3 4 A Q E 4 3 ENABLE Q F 5 2 LATCH SEIAL DATA INPUT A 4 SHIFT EGISTE LOGIC DIAGAM LATCH 5 Q A Q B 2 Q C 3 Q D 4 Q E 5 Q F 6 Q G 7 Q H PAALLEL DATA S Q G Q H SHIFT ESET SQ H SHIFT ESET LATCH ENABLE SQ H = PIN 6 = PIN 8 SEIAL DATA ODEING INFOMATION D2G Device Package Shipping SOIC 6 (Pb Free) 20 Tape & eel DT2G TSSOP 6* 20 Tape & eel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specificatio Brochure, BD80/D. *This package is inherently Pb Free. 2

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM ATINGS Symbol Parameter Value Unit DC Supply Voltage (eferenced to ) 0.5 to V V in DC Input Voltage (eferenced to ) 0.5 to V V out DC Output Voltage (eferenced to ) 0.5 to V I in DC Input Current, per Pin ±20 ma I out DC Output Current, per Pin ±35 ma I CC DC Supply Current, and Pi ± ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package 0 4 T stg Storage Temperature 65 to + C T L Lead Temperature, mm from Case for 0 Seconds (SOIC or TSSOP Package) 2 Stresses exceeding Maximum atings may damage the device. Maximum atings are stress ratings only. Functional operation above the ecommended Operating Conditio is not implied. Extended exposure to stresses above the ecommended Operating Conditio may affect device reliability. Derating SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). ECOMMENDED OPEATING CONDITIONS Symbol Parameter Min Max Unit DC Supply Voltage (eferenced to ) V V in, V out DC Input Voltage, Output Voltage (eferenced to ) mw C 0 V T A Operating Temperature, All Package Types C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be cotrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. t r, t f Input ise and Fall Time = V (Figure ) = V = V

4 DC ELECTICAL CHAACTEISTICS (Voltages eferenced to ) Symbol Parameter Test Conditio V IH V IL V OH V OL V OH V OL I in I OZ I CC Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage, Q A Q H Maximum Low Level Output Voltage, Q A Q H Minimum High Level Output Voltage, SQ H Maximum Low Level Output Voltage, SQ H Maximum Input Leakage Current Maximum Three State Leakage Current, Q A Q H Maximum Quiescent Supply Current (per Package) V out = 0. V or 0. V I out 20 A V out = 0. V or 0. V I out 20 A I out 20 A I out 20 A II out I 20 A II out I 20 A I out 2.4 ma I out ma I out 7.8 ma I out 2.4 ma I out ma I out 7.8 ma I out 2.4 ma II out I 4.0 ma II out I 5.2 ma I out 2.4 ma II out I 4.0 ma II out I 5.2 ma (V) Guaranteed Limit 55 to 25 C 85 C 25 C V in = or ±0. ±.0 ±.0 A Output in High Impedance State V in = V IL or V IH V out = or V in = or l out = 0 A Unit V ±0.25 ±2.5 ±2.5 A A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). V V V V V 4

5 AC ELECTICAL CHAACTEISTICS (C L = pf, Input t r = t f = ) Symbol f max t PLH, t PHL t PHL t PLH, t PHL t PLZ, t PHZ t PZL, t PZH t TLH, t THL t TLH, t THL Parameter Maximum Clock Frequency (% Duty Cycle) (Figures and 7) Maximum Propagation Delay, Shift Clock to SQ H (Figures and 7) Maximum Propagation Delay, eset to SQ H (Figures 2 and 7) Maximum Propagation Delay, Latch Clock to Q A Q H (Figures 3 and 7) Maximum Propagation Delay, Output Enable to Q A Q H (Figures 4 and 8) Maximum Propagation Delay, Output Enable to Q A Q H (Figures 4 and 8) Maximum Output Traition Time, Q A Q H (Figures 3 and 7) Maximum Output Traition Time, SQ H (Figures and 7) (V) Guaranteed Limit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance pf C out Maximum Three State Output Capacitance (Output in pf High Impedance State), Q A Q H NOTE: For propagation delays with loads other than pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D) C, = V C PD Power Dissipation Capacitance (Per Package)* 300 pf * Used to determine the no load dynamic power coumption: P D = C PD V 2 CC f + I CC. For load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). Unit MHz 5

6 TIMING EQUIEMENTS (Input t r = t f = ) Symbol Parameter (V) Guaranteed Limit 25 C to 55 C 85 C 25 C Unit t su Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5) t su Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) t h Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) t rec Minimum ecovery Time, eset Inactive to Shift Clock (Figure 2) t w Minimum Pulse Width, eset (Figure 2) t w Minimum Pulse Width, Shift Clock (Figure ) t w Minimum Pulse Width, Latch Clock (Figure 6) t r, t f Maximum Input ise and Fall Times (Figure )

7 Operation eset Serial Input A Inputs Shift Clock FUNCTION TABLE Latch Clock Output Enable Shift egister Contents esulting Function Latch egister Contents Serial Output SQ H eset shift register L X X L, H, L L U L U Shift data into shift register Shift register remai unchanged Trafer shift register contents to latch register Latch register remai unchanged Parallel Outputs Q A Q H H D L, H, L D S A ; S N S N+ U S G S H U H X L, H, L, H, L U U U U H X L, H, L U S N L N U S N X X X L, H, L * U * U Enable parallel outputs X X X X L * ** * Enabled Force outputs into high X X X X H * ** * Z impedance state S = shift register contents D = data (L, H) logic level = Low to High * = depends on eset and Shift Clock inputs L = latch register contents U = remai unchanged = High to Low ** = depends on Latch Clock input PIN DESCIPTIONS INPUTS A (Pin 4) Serial Data Input. The data on this pin is shifted into the 8 bit serial shift register. CONTOL INPUTS Shift Clock (Pin ) Shift egister Clock Input. A low to high traition on this input causes the data at the Serial Input pin to be shifted into the 8 bit shift register. eset (Pin 0) Active low, Asynchronous, Shift egister eset Input. A low on this pin resets the shift register portion of this device only. The 8 bit latch is not affected. Latch Clock (Pin 2) Storage Latch Clock Input. A low to high traition on this input latches the shift register data. Output Enable (Pin 3) Active low Output Enable. A low on this input allows the data from the latches to be presented at the outputs. A high on this input forces the outputs (Q A Q H ) into the high impedance state. The serial output is not affected by this control unit. S Q A Q H (Pi 5,, 2, 3, 4, 5, 6, 7) Noninverted, 3 state, latch outputs. SQ H (Pin 9) Noninverted, Serial Data Output. This is the output of the eighth stage of the 8 bit shift register. This output does not have three state capability. 7

8 SWITCHING WAVEFOMS t r t f t w SHIFT 90% % 0% t w ESET t PHL % SQ H 90% % 0% t PLH /fmax t TLH t PHL t THL SQ H SHIFT % t rec % Figure. Figure 2. LATCH Q A Q H S 90% % 0% % t PLH t TLH t PHL t THL ENABLE Q Q % t PZL % t PZH % t PLZ t PHZ 0% 90% HIGH IMPEDANCE V OL V OH HIGH IMPEDANCE Figure 3. Figure 4. SEIAL INPUT A SWITCH VALID % t su t h % SHIFT LATCH % t su % t w Figure 5. Figure 6. TEST CICUITS TEST POINT TEST POINT DEVICE UNDE TEST C L * DEVICE UNDE TEST k C L * CONNECT TO WHEN TESTING t PLZ AND t PZL. CONNECT TO WHEN TESTING t PHZ AND t PZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 7. Figure 8. 8

9 EXPANDED LOGIC DIAGAM ENABLE 3 LATCH 2 SEIAL DATA INPUT A 4 D Q S A L A 5 Q A D Q S B L B Q B D Q S C L C 2 Q C S D L D S E L E 3 4 Q D Q E PAALLEL DATA S D Q S F L F 5 Q F D Q S G L G 6 Q G SHIFT D Q S H L H 7 Q H ESET 0 9 SEIAL DATA SQ H 9

10 TIMING DIAGAM SHIFT SEIAL DATA INPUT A ESET LATCH ENABLE Q A Q B Q C Q D Q E Q F Q G Q H SEIAL DATA SQ H NOTE: implies that the output is in a high impedance state. 0

11 PACKAGE DIMENSIONS SOIC 6 CASE B 05 ISSUE K A B P 8 PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLEANCING PE ANSI YM, CONTOLLING DIMENSION: MILLIMETE. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD POTUSION. 4. MAXIMUM MOLD POTUSION 0.5 (0.006) PE SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATEIAL CONDITION. T SEATING PLANE G D 6 PL K C M X 45 J F MILLIMETES INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC 0.0 BSC J K M P (0.00) M T B S A S SOLDEING FOOTPINT* 8X X.2 6 6X PITCH 8 9 DIMENSIONS: MILLIMETES *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D.

12 PACKAGE DIMENSIONS TSSOP 6 CASE 948F 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C 6X K EF 0.0 (0.004) M T U S V S A V G B U H J N N J F DETAIL E DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N 0.25 (0.00) M W NOTES:. DIMENSIONING AND TOLEANCING PE ANSI YM, CONTOLLING DIMENSION: MILLIMETE. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. POTUSIONS O GATE BUS. MOLD FLASH O GATE BUS SHALL NOT EXCEED 0.5 (0.006) PE SIDE. 4. DIMENSION B DOES NOT INCLUDE INTELEAD FLASH O POTUSION. INTELEAD FLASH O POTUSION SHALL NOT EXCEED 0.25 (0.00) PE SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATEIAL CONDITION. 6. TEMINAL NUMBES AE SHOWN FO EFEENCE ONLY. 7. DIMENSION A AND B AE TO BE DETEMINED AT DATUM PLANE W. MILLIMETES INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDEING FOOTPINT* PITCH 6X X.26 DIMENSIONS: MILLIMETES *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. 2

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