MC74VHC245. Octal Bus Buffer/Line Driver

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MC74HC245 Octal Bus Buffer/Line Driver The MC74HC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology.

1 MC74HC245 Octal Bus Buffer/Line Driver The MC74HC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. It is intended for two way asynchronous communication between data buses. The direction of data transmission is determined by the level of the DIR input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated. All inputs are equipped with protection circuits against static discharge. High Speed: t PD = 4.0 ns (Typ) at CC = 5 Low Power Dissipation: I CC = 4 μa (Max) at T A = 25 C High Noise Immunity: NIH = NIL = 28% CC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range Low Noise: OLP =.2 (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 ma ESD Performance: HBM > 00 ; Machine Model > 0 Chip Complexity: 308 FETs or 77 Equivalent Gates These Devices are Pb Free and are RoHS Compliant APPLICATION NOTES Do not force a signal on an I/O pin when it is an active output, damage may occur. All floating (high impedance) input or I/O pins must be fixed by means of pull up or pull down resistors or bus terminator ICs. A parasitic diode is formed between the bus and CC terminals. Therefore, the HC245 cannot be used to interface 5 to 3 systems directly. SOIC DW SUFFIX CASE 75D TSSOP DT SUFFIX CASE 948E ORDERING INFORMATION Device Package Shipping MC74HC245DWG SOIC 38 Units/Rail MARKING DIAGRAMS HC245 AWLYYWWG HC 245 ALYW HC245 = Specific Device Code A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) MC74HC245DTG TSSOP 75 Units/Rail MC74HC245DWR2G SOIC 000 Units/Reel MC74HC245DTR2G TSSOP 2500 Units/T&R For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD80/D. Semiconductor Components Industries, LLC, May, Rev. 6 Publication Order Number: MC74HC245/D

2 MC74HC245 A DATA PORT A A2 A3 A4 A5 A6 A7 A8 DIR OE B 7 B2 6 B3 5 B4 4 B5 3 B6 2 B7 B8 B DATA PORT DIR A 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND CC OE B B2 B3 B4 B5 B6 B7 B8 Figure. LOGIC DIAGRAM Figure 2. PIN ASSIGNMENT FUNCTION TABLE Control Inputs OE DIR Operation L L Data Transmitted from Bus B to Bus A L H Data Transmitted from Bus A to Bus B H X Buses Isolated (High Impedance State) 2

3 MC74HC245 Î MAXIMUM RATINGS* Symbol Parameter Î alue Î Unit CC DC Supply oltage Î 0.5 to + 7.0Î in DC Input oltage Î 0.5 to + 7.0Î out DC Output oltage Î 0.5 to CC + 0.5Î I IK Input Diode Current Î Î ma I OK Output Diode Current Î ± Î ma I out DC Output Current, per Pin Î ± 25 Î ma I CC DC Supply Current, CC and GND Pins Î ± 75 Î ma P D Power Dissipation in Still Air SOIC Packages Î 500 Î mw TSSOP Package 450 Î T stg Storage Temperature Î 65 to + 50 Î C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Derating SOIC Packages: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Î Symbol Parameter Î Min Max Unit CC Î DC Supply oltage Î Î in Î DC Input oltage Î Î out Î DC Output oltage Î 0 CC Î T A Î Operating Temperature Î C t r, t f Î Input Rise and Fall Time CC = 3.3 ±0.3 Î 0 CC =5.0 ±0.5 Î 0 00 Î ns/ DC ELECTRICAL CHARACTERISTICS Î T A = 25 C T A = 40 to 85 C CC Symbol Parameter Test Conditions Min Typ Max Min Max Unit Î IH Minimum High Level Î Input oltage Î 3.0 to CC x 0.7Î CC x 0.7Î 5.5 IL Î Maximum Low Level Î 2.0 Î Input oltage 3.0 to 5.5 Î CC x 0.3 CC x 0.3 OH Î Minimum High Level Î in = IH or IL Output oltage Î I OH = 50μA Î Î Î in = IH or IL I OH = 4mA I OH = 8mAÎ Î Î 3.80 Î OL Î Maximum Low Level Î in = IH or IL Î Output oltage I OL = 50μA Î in = IH or IL I OL = 4mAÎ 3.0 Î I OL = 8mA I in Maximum Input Î Î in = 5.5 or GND 0 to 5.5 ± 0. ±.0 μa Leakage Current (DIR, OE) 3

4 MC74HC245 Î DC ELECTRICAL CHARACTERISTICS T A = 25 C Î T A = 40 to 85 C Î CC Symbol Î Parameter Î Test Conditions Min Î Typ Max Min Max Unit I OZ Î Maximum Î in = IL or IH Î 5.5 Three State Leakage out = CC or GND Î Î ± 0.25 ± 2.5 μa Current I CC Î Î Maximum Quiescent in = CC or GND 5.5 Supply Current Î Î μa AC ELECTRICAL CHARACTERISTICS (Input t r = t f = 3.0ns) Î T Î A = 25 C T A = 40 to 85 C Î Symbol Parameter Test Conditions Min Typ Max Min Max Unit Î t PLH, Maximum Propagation Delay, t PHL CC = 3.3 ± 0.3 C L = 5pF A to B or B to A C L ns Î = 50pF Î CC = 5.0 ± 0.5 C L = 5pF Î C L = 50pF Î t PZL, Î Output Enable Time CC = 3.3 ± 0.3 C L = 5pF t PZH OE to A or B R L = kω C L = 50pF Î Î Î ns Î Î CC = 5.0 ± 0.5 C L = 5pF R L = kω C L = 50pF Î t PLZ, Output Disable Time CC = 3.3 ± 0.3 C L = 50pF t PHZ Î OE to A or B R L = kω.5î ns Î Î CC = 5.0 ± 0.5 C L = 50pF Î R Î L = kω Î t OSLH, Î Output to Output Skew CC = 3.3 ± 0.3 C L = 50pF Î.5.5 ns t OSHL (Note ) Î Î CC = 5.0 ± 0.5 C L = 50pF.0.0 (Note ) Î ns C in Î Maximum Input Capacitance DIR, OE Î pf C I/O Î Maximum Three State Î 8 pf I/O Capacitance 25 C, CC = 5.0 C PD Power Dissipation Capacitance (Note 2) 2 pf. Parameter guaranteed by design. t OSLH = t PLHm t PLHn, t OSHL = t PHLm t PHLn. 2. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC / 8 (per bit). C PD is used to determine the no load dynamic power consumption; P D = C PD 2 CC f in + I CC CC. NOISE CHARACTERISTICS (Input t r = t f = 3.0ns, C L = 50pF, CC = 5.0) Symbol Parameter T A = 25 C OLP Quiet Output Maximum Dynamic OL OL Quiet Output Minimum Dynamic OL IHD Minimum High Level Dynamic Input oltage 3.5 ILD Maximum Low Level Dynamic Input oltage.5 Typ Max Unit 4

5 MC74HC245 SWITCHING WAEFORMS DIR 50% CC GND A or B B or A t PLH 50% 50% CC t PHL CC GND OE A or B A or B 50% CC t PZL 50% CC t PZH 50% CC t PLZ t PHZ 50% CC CC GND HIGH IMPEDANCE OL +0.3 OH -0.3 HIGH IMPEDANCE Figure 3. Figure 4. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C L * DEICE UNDER TEST OUTPUT kω C L * CONNECT TO CC WHEN TESTING t PLZ AND t PZL. CONNECT TO GND WHEN TESTING t PHZ AND t PZH. *Includes all probe and jig capacitance Figure 5. *Includes all probe and jig capacitance Figure 6. 5

6 MC74HC245 A A2 A3 A4 A5 A6 A7 A B B2 B3 B4 B5 B6 B7 B8 DIR OE 9 Figure 7. EXPANDED LOGIC DIAGRAM DIR, OE A, B INPUT I/O Figure 8. INPUT EQUIALENT CIRCUIT Figure 9. BUS TERMINAL EQUIALENT CIRCUIT 6

7 MC74HC245 PACKAGE DIMENSIONS SOIC CASE 75D 05 ISSUE G D A H 0X 0.25 M B M 0 E h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y4.5M, DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. X B 0.25 M T A S 8X e B B S A A T SEATING PLANE C L MILLIMETERS DIM MIN MAX A A B C D E e.27 BSC H h L

8 MC74HC245 PACKAGE DIMENSIONS 0.5 (0.006) T L 0.5 (0.006) T U 2X L/2 PIN IDENT U S S C 0.00 (0.004) T SEATING PLANE X K REF 0.0 (0.004) M T U S S 0 A D G H TSSOP CASE 948E 02 ISSUE C B U N J J N SOLDERING FOOTPRINT 7.06 K K ÍÍÍÍ ÍÍÍÍ SECTION N N 0.25 (0.00) M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. F MILLIMETERS INCHES DIM MIN MAX MIN MAX DETAIL E A B C W D F G 0.65 BSC BSC H J DETAIL E J K K L 6.40 BSC BSC M PITCH 6X X.26 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74HC245/D

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