MC74VHCT125A. Quad Bus Buffer. with 3 State Control Inputs

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1 M4HT25A Quad Bus Buffer with 3 State ontrol Inputs The M4HT25A is a high speed MOS quad bus buffer fabricated with silicon gate MOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining MOS low power dissipation. The M4HT25A requires the 3 state control input (OE) to be set High to place the output into the high impedance state. The HT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5.0 MOS level output swings. The HT25A input structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. The output structures also provide protection when = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to.0, allowing the interface of 5.0 systems to 3.0 systems. SOI 4 D SUFFIX ASE 5A TSSOP 4 DT SUFFIX ASE 948G 4 MARKING DIAGRAMS 4 HT25AG AWLYWW HT 25A ALYW Features High Speed: t PD = 3.8 ns (Typ) at = 5.0 Low Power Dissipation: I = 4.0 A (Max) at T A = 25 TTL ompatible Inputs: IL = 0.8 ; IH = 2.0 Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 to 5.5 Operating Range Low Noise: OLP = 0.8 (Max) Pin and Function ompatible with Other Standard Logic Families Latchup Performance Exceeds 300 ma ESD Performance: Human Body Model > 2000 ; Machine Model > 200 hip omplexity: 2 FETs or 8 Equivalent Gates Pb Free Packages are Available* SOEIAJ 4 M SUFFIX ASE 965 A = Assembly Location L, WL = Wafer Lot Y, YY = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 4 HT25 ALYWG *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor omponents Industries, LL, 2006 January, 2006 Rev. Publication Order Number: M4HT25A/D

2 M4HT25A PIN ONNETION (Top iew) LOGI DIAGRAM Active Low Output Enables OE A Y OE2 A2 Y OE4 A4 Y4 OE3 A3 A OE A2 OE Y Y2 GND 8 Y3 A3 OE Y3 FUNTION TABLE HT25A Inputs Output A OE Y A4 OE4 2 3 Y4 H L H L L L X H Z ORDERING INFORMATION Device Package Shipping M4HT25ADR2 SOI Tape & Reel M4HT25ADR2G SOI 4 (Pb Free) 2500 Tape & Reel M4HT25ADTR2 TSSOP 4* 2500 Tape & Reel M4HT25ADTRG TSSOP 4* 2500 Tape & Reel M4HT25AM SOEIAJ 4 50 Units / Rail M4HT25AMG SOEIAJ 4 (Pb Free) 50 Units / Rail M4HT25AMEL SOEIAJ Tape & Reel M4HT25AMELG SOEIAJ 4 (Pb Free) 2000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 M4HT25A Î MAXIMUM RATINGS Symbol Parameter Î alue Î Unit D Supply oltage Î 0.5 to +.0 Î in D Input oltage 0.5 to +.0 Î out D Output oltage Output in 3 State 0.5 to +.0 High or Low State Î 0.5 to +0.5 Î I IK Input Diode urrent Î 20 Î ma I OK Output Diode urrent ( OUT < GND; OUT > ) Î 20 Î ma I out D Output urrent, per Pin Î 25 Î ma I D Supply urrent, and GND Pins 5 ma Î P D Power Dissipation in Still Air, SOI Packages 500 TSSOP Package Î 450 Î mw Î T stg Storage Temperature 65 to +50 Î Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating SOI Packages: mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. REOMMENDED OPERATING ONDITIONS Î Î Î Symbol Parameter Min Max Unit D Supply oltage Î 4.5 Î 5.5 Î in D Input oltage Î 0 Î 5.5 out D Output oltage Output in 3 State Î 0 Î 5.5Î High or Low State 0 Î Î T A Operating Temperature Î Î Î Input Rise and Fall Time = Î ns/ t r, t f Î D ELETRIAL HARATERISTIS Î SymbolÎ Parameter Test onditionsî T A = 25 T A 85 Î T A 25 () Î Min Î Typ Î Max Î Min Max Î Min Î Max Unit IH Î Minimum High Level Input oltage Î Î 3.0Î.2Î 4.5 Î 5.5Î 2.0Î Î Î Î.2.2Î 2.0 Î Î IL Î Maximum Low Level Input oltage Î Î 3.0Î 4.5 Î 5.5Î Î Î 0.53 Î 0.8 Î 0.8 Î 0.53 Î Î Î Î 0.8 OH Î Minimum High Level Output IN = IH or IL Î 3.0 oltage Î 2.9Î 3.0 Î I OH = 50 A IN = IH or IL Î IN = IH or IL I OH = 4.0 ma Î 3.0Î 2.58Î I OH = 8.0 ma Î OL Maximum Low Level Output Î oltage IN = IH or IL I OL = 50 A Î Î Î Î Î Î Î 0. Î Î Î Î Î IN = IH or IL IN = IH or IL Î Î Î Î I Î OL = 4.0 ma I OL = 8.0 ma Î Î Î Î 0.52 I IN Î Maximum Input Leakage urrent IN = 5.5 or GNDÎ 0 toî 0. 0.Î A 5.5 Î I Maximum Quiescent Supply Î urrent IN = or GND Î Î Î Î 20 Î Î 40 A I T Î Quiescent Supply urrent Input: IN = 3.4 Î 5.5 Î Î.65 ma I OZ Î Maximum Three State Leakage IN = IH or Î 5.5Î urrent Î IL OUT = or GND Î Î Î Î 0.25Î Î Î 2.5Î Î 2.5 A I OPD Î Output Leakage urrent OUT = 5.5 Î 0.0Î Î 0 A 3

4 M4HT25A Î A ELETRIAL HARATERISTIS (Input t r = t f = 3.0 ns) T A = 25 T A = 85 T A 25 Symbol Parameter Î Test onditions MinÎ Typ Max MinÎ MaxÎ Min Max Unit t PLH, Maximum Propagation Delay, Î = L = 5 pf Î Î Î ns t PHL A to Y L = 50 pf Î Î Î = L = 5 pf Î 3.8 L = 50 pf Î t PZL, Maximum Output Enable = L Î = 5 pf t PZH TIme,OE to Y Î R L =.0 k L = 50 pf Î Î Î Î Î.5 ns 5.0 Î = L = 5 pf Î Î R Î L =.0 k L = 50 pf Î Î Î.0Î t PLZ, Maximum Output Disable t PHZ = L = 50 pf Time,OE to Y R L Î ns =.0 k Î Î = L = 50 pf R L =.0 k Î Î Î Î 0.0Î Î 2.0 t OSLH, Output to Output Skew Î = L = 50 pf Î Î t OSHL (Note ) Î ns Î = L = 50 pf (Note ) Î Î in Maximum Input apacitance pf out Maximum Three State Output apacitance (Output in HighÎ Î 6 pf Î Impedance State) Î PD Power Dissipation apacitance (Note 2) 25, = 5.0. Parameter guaranteed by design. t OSLH = t PLHm t PLHn, t OSHL = t PHLm t PHLn. 2. PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I (OPR) = PD f in + I / 4 (per buffer). PD is used to determine the no load dynamic power consumption; P D = PD 2 f in + I. NOISE HARATERISTIS (Input t r = t f = 3.0 ns, L = 50 pf, = 5.0 ) Symbol haracteristic 4 T A = 25 OLP Quiet Output Maximum Dynamic OL OL Quiet Output Minimum Dynamic OL IHD Minimum High Level Dynamic Input oltage 3.5 ILD Maximum Low Level Dynamic Input oltage.5 Typ Max pf Unit 4

5 M4HT25A SWITHING WAEFORMS A Y t PLH.5.5 t PHL 3.0 GND OH OL Figure. OE Y Y.5 t PZL t PLZ.5 t PZH t PHZ.5 Figure GND HIGH IMPEDANE OL OH 0.3 HIGH IMPEDANE TEST POINT DEIE UNDER TEST OUTPUT L * *Includes all probe and jig capacitance Figure 3. Test ircuit DEIE UNDER TEST TEST POINT k OUTPUT L * ONNET TO WHEN TESTING t PLZ AND t PZL. ONNET TO GND WHEN TESTING t PHZ AND t PZH. *Includes all probe and jig capacitance Figure 4. Test ircuit 5

6 M4HT25A PAKAGE DIMENSIONS SOI 4 D SUFFIX ASE 5A 03 ISSUE G T SEATING PLANE G A 4 8 D 4 PL B K P PL 0.25 (0.00) M T B S A S 0.25 (0.00) M B M R X 45 M J F NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G.2 BS BS J K M 0 0 P R TSSOP 4 DT SUFFIX ASE 948G 0 ISSUE A 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D 4 4X K REF 0.0 (0.004) M T U S S N (0.00) M B U A G H N J J F DETAIL E K K ÇÇÇ ÉÉÉ ÇÇÇ SETION N N DETAIL E W NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K DIMENSION AT MAXIMUM MATERIAL ONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G 0.65 BS BS H J J K K L 6.40 BS BS M

7 M4HT25A PAKAGE DIMENSIONS SOEIAJ 4 M SUFFIX ASE ISSUE A e 4 8 Z D E A H E IEW P M L E Q L DETAIL P NOTES: М. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, 982. М 2. ONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXEED 0.5 (0.006) PER SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL ONDITION. DAMBAR ANNOT BE LOATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPAE BETWEEN PROTRUSIONS AND ADJAENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INHES A b A A DIM MIN MAX MIN MAX 0.3 (0.005) M 0.0 (0.004) b c D E e.2 BS BS H E L E M Q Z c ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Japan: ON Semiconductor, Japan ustomer Focus enter 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. M4HT25A/D