MC14020B. 14-Bit Binary Counter

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M4020B 4-Bit Binary ounter The M4020B 4stage binary counter is cotructed with MOS Phannel and Nhannel enhancement mode devices in a single monolithic structure.

1 M4020B 4-Bit Binary ounter The M4020B 4stage binary counter is cotructed with MOS Phannel and Nhannel enhancement mode devices in a single monolithic structure. This part is designed with an input wave shaping circuit and 4 stages of ripplecarry binary counter. The device advances the count on the negativegoing edge of the clock pulse. Applicatio include time delay circuits, counter controls, and frequencydividing circuits. Features Fully Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 to 8 apable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range Buffered Outputs Available from stages and 4 thru 4 ommon Reset Line PinforPin Replacement for D4020B These are PbFree Devices MAXIMUM RATINGS (Voltages Referenced to V SS ) Symbol Parameter Value Unit V DD D Supply Voltage Range 0.5 to +8.0 V V in, V out I in, I out P D Input or Output Voltage Range (D or Traient) Input or Output urrent (D or Traient) per Pin Power Dissipation, per Package (Note ) 0.5 to V DD V ± ma 500 mw T A Ambient Temperature Range 55 to +25 T stg Storage Temperature Range 65 to +0 T L Lead Temperature (8Second Soldering) 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditio is not implied. Extended exposure to stresses above the Recommended Operating onditio may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ From 65 To 25 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. PDIP6 P SUFFIX ASE 648 SOI6 D SUFFIX ASE 75B TSSOP6 DT SUFFIX ASE 948F SOEIAJ6 F SUFFIX ASE 966 MARKING DIAGRAMS M4020BP AWLYYWWG 4020BG AWLYWW M4020B ALYWG A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = PbFree Indicator (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet B ALYW *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor omponents Industries, LL, 2009 October, 2009 Rev. 6 Publication Order Number: M4020B/D

2 M4020B PIN ASSIGNMENT V DD R 4 7 V SS 8 9 TRUTH TABLE lock Reset Output State 0 No hange 0 Advance to Next State X All Outputs are Low X = Don t are LOGI DIAGRAM LOK R R R R R R RESET 6 = PIN 4 7 = PIN 6 8 = PIN 3 9 = PIN 2 = PIN 4 = PIN V DD = PIN 6 V SS = PIN 8 ORDERING INFORMATION M4020BPG M4020BDG M4020BDR2G Device Package Shipping PDIP6 (PbFree) SOI6 (PbFree) SOI6 (PbFree) 500 Units / Rail 48 Units / Rail 2500 Units / Tape & Reel M4020BDTG TSSOP6* 96 Units / Rail M4020BFELG SOEIAJ6 (PbFree) 2000 Units / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently PbFree. 2

3 M4020B ELETRIAL HARATERISTIS (Voltages Referenced to V SS ) Output Voltage V in = V DD or 0 haracteristic Symbol V DD V in = 0 or V DD 0 Level Level Input Voltage 0 Level (V O = 4.5 or 0.5 ) (V O = 9.0 or.0 ) (V O = 3.5 or.5 ) (V O = 0.5 or 4.5 ) (V O =.0 or 9.0 ) (V O =.5 or 3.5 ) Level Output Drive urrent (V OH = 2.5 ) Source (V OH = 4.6 ) (V OH = 9.5 ) (V OH = 3.5 ) (V OL = 0.4 ) Sink (V OL = 0.5 ) (V OL =.5 ) V OL V OH V IL V IH I OH I OL Min Max Min Typ (Note 2) Max Min Max Input urrent I in ± 0. ± ± 0. ±.0 Adc Input apacitance (V in = 0) in 7.5 pf Unit madc madc uiescent urrent (Per Package) Total Supply urrent (Notes 3 & 4) (Dynamic plus uiescent, Per Package) ( L = 50 pf on all outputs, all buffers switching) I DD I T I T = (0.42 A/kHz)f + I DD I T = (0.85 A/kHz)f + I DD I T = (.43 A/kHz)f + I DD 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. 3. The formulas given are for the typical characteristics only at To calculate total supply current at loads other than 50 pf: I T ( L ) = I T (50 pf) + ( L 50) Vfk where: I T is in A (per package), L in pf, V = (V DD V SS ) in volts, f in khz is input frequency, and k = Adc Adc 3

4 M4020B SWITHING HARATERISTIS (Note 5) ( L = 50 pf, T A = 25 ) haracteristic Symbol V DD Min Typ (Note 6) Max Unit Output Rise and Fall Time t TLH, t THL = (.5 /pf) L + 25 t TLH, t THL = (0.75 /pf) L t TLH, t THL = (0.55 /pf) L t TLH, t THL Propagation Delay Time lock to t PHL, t PLH = (.7 /pf) L + 75 t PHL, t PLH = (0.66 /pf) L + 82 t PHL, t PLH = (0.5 /pf) L + 55 t PLH, t PHL lock to 4 t PHL, t PLH (.7 /pf) L t PHL, t PLH = (0.66 /pf) L t PHL, t PLH = (0.5 /pf) L Propagation Delay Time Reset to n t PHL = (.7 /pf) L t PHL = (0.66 /pf) L + 22 t PHL = (0.5 /pf) L + 90 t PHL lock Pulse Width t WH lock Pulse Frequency f max lock Rise and Fall Time t TLH, t THL Reset Pulse Width t WL Reset Recovery Time t rec No Limit 5. The formulas given are for the typical characteristics only at Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance MHz 4

5 M4020B PULSE GENERATOR LOK 500 F R V DD 0.0 F ERAMI Figure. Power Dissipation Test ircuit and Waveform I D 4 n VSS L % 50% % 50% DUTY YLE L V DD V SS L PULSE GENERATOR R V DD 4 n V SS L L L LOK 90% 50% % t WH t PLH t TLH 90% 50% % t THL t PHL Figure 2. Switching Time Test ircuit and Waveforms LOK ,384 RESET Figure 3. Timing Diagram 5

6 M4020B PAKAGE DIMENSIONS PDIP6 P SUFFIX PLASTI DIP PAKAGE ASE ISSUE T 6 A 8 9 B NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MOLD FLASH. 5. ROUNDED ORNERS OPTIONAL. H G F D 6 PL S K 0.25 (0.0) M T SEATING T PLANE A M J L M INHES MILLIMETERS DIM MIN MAX MIN MAX A B D F G 0.0 BS 2.54 BS H 0 BS.27 BS J K L M 0 0 S SOI6 D SUFFIX PLASTI SOI PAKAGE ASE 75B05 ISSUE K A B P 8 PL 0.25 (0.0) M B S NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. T SEATING PLANE G D 6 PL K M R X 45 J F MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G.27 BS 0 BS J K M P R (0.0) M T B S A S 6

7 M4020B PAKAGE DIMENSIONS 0. (0.006) T 0. (0.006) T 0. (0.004) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 6X K REF A V G TSSOP6 DT SUFFIX PLASTI TSSOP PAKAGE ASE 948F0 ISSUE B 0. (0.004) M T U S V S B U H J N N J F DETAIL E DETAIL E K K ÇÇÇ ÉÉÉ SETION NN 0.25 (0.0) M SOLDERING FOOTPRINT 7.06 NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXEED 0. (0.006) PER SIDE. 4. DIMENSION B DOES NOT INLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXEED 0.25 (0.0) PER SIDE. 5. DIMENSION K DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K DIMENSION AT MAXIMUM MATERIAL ONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. W MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G 0.65 BS BS H J J K K L 6.40 BS BS M PITH 6X X.26 DIMENSIONS: MILLIMETERS 7

8 M4020B PAKAGE DIMENSIONS SOEIAJ6 F SUFFIX PLASTI EIAJ SOI PAKAGE ASE 9660 ISSUE A e 6 9 Z b D A H E A 0.3 (0.005) M 0. (0.004) 8 E VIEW P M L E L DETAIL P c NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXEED 0. (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL ONDITION. DAMBAR ANNOT BE LOATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPAE BETWEEN PROTRUSIONS AND ADJAENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INHES DIM MIN MAX MIN MAX A A b c D E e.27 BS 0 BS H E L L E M Z ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@oemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative M4020B/D

MC14584B. Hex Schmitt Trigger

MC14584B. Hex Schmitt Trigger MC4584B Hex Schmitt Trigger The MC4584B Hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where