MC14516B. Binary Up/Down Counter

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1 M456B Binary Up/Down ounter The M456B synchronous up/down binary counter is cotructed with MOS Pchannel and Nchannel enhancement mode devices in a monolithic structure. This counter can be preset by applying the desired value, in binary, to the Preset inputs (P0, P, P2, P3) and then bringing the Preset Enable () high. The direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive traition of the clock input. ascading can be accomplished by connecting the arry Out to the arry In of the next stage while clocking each counter in parallel. The outputs (0,, 2, 3) can be reset to a low state by applying a high to the reset (R) pin. This MOS counter finds primary use in up/down and difference counting. Other applicatio include: () Frequency synthesizer applicatio where low power dissipation and/or high noise immunity is desired, (2) AnalogtoDigital and DigitaltoAnalog conversio, and (3) Magnitude and sign generation. Features Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 8 Vdc Internally Synchronous for High Speed Logic Edgelocked Design ount Occurs on Positive Going Edge of lock Single Pin Reset Asynchronous Preset Enable Operation apable of Driving Two LowPower TTL Loads or One LowPower Schottky Load Over the Rated Temperature Range These Devices are PbFree and are RoHS ompliant NLV Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE0 ualified and PPAP apable MAXIMUM RATINGS (Voltages Referenced to V SS ) Parameter Symbol Value Unit D Supply Voltage Range 0.5 to +8.0 V Input or Output Voltage Range (D or Traient) Input or Output urrent (D or Traient) per Pin V in, V out 0.5 to I in, I out ± ma Power Dissipation, per Package (Note ) P D 500 mw Ambient Temperature Range T A 55 to +25 Storage Temperature Range T stg 65 to +0 Lead Temperature (8Second Soldering) T L 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditio is not implied. Extended exposure to stresses above the Recommended Operating onditio may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ From 65 To 25 V PDIP6 P SUFFIX ASE SOI6 D SUFFIX ASE 75B SOEIAJ6 F SUFFIX ASE 966 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = PbFree Package MARKING DIAGRAMS 456BG AWLYWW ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range V SS (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or ). Unused outputs must be left open. 6 6 M456BP AWLYYWWG M456B ALYWG Semiconductor omponents Industries, LL, 203 May, 203 Rev. 9 Publication Order Number: M456B/D

2 M456B PIN ASSIGNMENT BLOK DIAGRAM 3 P3 P0 ARRY IN 0 ARRY OUT V SS P2 P U/D R ARRY IN UP/DOWN P0 P P2 P ARRY OUT = PIN 6 V SS = PIN 8 TRUTH TABLE arry In Up/Down Preset Enable Reset lock Action X 0 0 X No ount ount Up ount Down X X 0 X Preset X X X X Reset X = Don t are NOTE: When counting up, the arry Out signal is normally high and is low only when 0 through 3 are high and arry In is low. When counting down, arry Out is low only when 0 through 3 and arry In are low. ORDERING INFORMATION Device Package Shipping M456BPG PDIP6 (PbFree) 25 Units / Rail M456BDG SOI6 (PbFree) 48 Units / Rail M456BDR2G NLV456BDR2G* M456BFELG SOI6 (PbFree) SOEIAJ6 (PbFree) 2500 / Tape & Reel 0 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *NLV Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE0 ualified and PPAP apable. 2

3 M456B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELETRIAL HARATERISTIS (Voltages Referenced to V SS ) haracteristic Output Voltage 0 Level V in = or 0 V in = 0 or Level Input Voltage 0 Level (V O = 4.5 or 0.5 Vdc) (V O = 9.0 or.0 Vdc) (V O = 3.5 or.5 Vdc) Level (V O = 0.5 or 4.5 Vdc) (V O =.0 or 9.0 Vdc) (V O =.5 or 3.5 Vdc) Output Drive urrent (V OH = 2.5 Vdc) Source (V OH = 4.6 Vdc) (V OH = 9.5 Vdc) (V OH = 3.5 Vdc) (V OL = 0.4 Vdc) Sink (V OL = 0.5 Vdc) (V OL =.5 Vdc) Symbol Vdc V OL V OH V IL V IH I OH I OL Min Max Min Typ (Note 2) Max Min Max Input urrent I in ± 0. ± ± 0. ±.0 Adc Input apacitance (V in = 0) in 7.5 pf uiescent urrent (Per Package) I DD Total Supply urrent (Note 3, 4) (Dynamic plus uiescent, Per Package) ( L = 50 pf on all outputs, all buffers switching) I T I T = (0.58 A/kHz) f + I DD I T = (.20 A/kHz) f + I DD I T = (.70 A/kHz) f + I DD 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. 3. The formulas given are for the typical characteristics only at To calculate total supply current at loads other than 50 pf: I T ( L ) = I T (50 pf) + ( L 50) Vfk where: I T is in A (per package), L in pf, V = ( V SS ) in volts, f in khz is input frequency, and k = Unit Vdc Vdc Vdc Vdc madc madc Adc Adc 3

4 M456B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITHING HARATERISTIS (Note 5) ( L = 50 pf, T A = 25 ) Output Rise and Fall Time t TLH, t THL = (.5 /pf) L + 25 t TLH, t THL = (0.75 /pf) L t TLH, t THL = (0.55 /pf) L Propagation Delay Time lock to t PLH, t PHL = (.7 /pf) L t PLH, t PHL = (0.66 /pf) L + 97 t PLH, t PHL = (0.5 /pf) L + 75 lock to arry Out t PLH, t PHL = (.7 /pf) L t PLH, t PHL = (0.66 /pf) L + 97 t PLH, t PHL = (0.5 /pf) L + 75 arry In to arry Out t PLH, t PHL = (.7 /pf) L t PLH, t PHL = (0.66 /pf) L + 97 t PLH, t PHL = (0.5 /pf) L + 75 Preset or Reset to t PLH, t PHL = (.7 /pf) L t PLH, t PHL = (0.66 /pf) L + 97 t PLH, t PHL = (0.5 /pf) L + 75 Preset or Reset to arry Out t PLH, t PHL = (.7 /pf) L t PLH, t PHL = (0.66 /pf) L + 92 t PLH, t PHL = (0.5 /pf) L + 25 All Types haracteristic Symbol Min Typ (Note 6) Max t TLH, t THL t PLH, t PHL t PLH, t PHL t PLH, t PHL t PLH, t PHL t PLH, t PHL Unit Reset Pulse Width t w lock Pulse Width t WH lock Pulse Frequency f cl Preset or Reset Removal Time The Preset or Reset signal must be low prior to a positivegoing traition of the clock. t rem lock Rise and Fall Time t TLH, t THL Setup Time arry In to lock Hold Time lock to arry In Setup Time Up/Down to lock Hold Time lock to Up/Down Setup Time Pn to Hold Time to Pn t su t h t su t h t su t h Preset Enable Pulse Width t WH The formulas given are for the typical characteristics only at Data labelled Typ is not to be used for design purposes but is intended as an Indication of the I s potential performance MHz s 4

5 M456B 500 pf I D 0.0 F ERAMI 0 PULSE GENERATOR ARRY IN R UP/DOWN P0 P P2 P3 2 3 ARRY OUT L L L L 20 50% VARIABLE WIDTH 90% % 20 V SS L Figure. Power Dissipation Test ircuit and Waveform LOGI DIAGRAM P P 2 P P P ENABLE P P P P ARRY OUT 7 T T T T ARRY IN 5 UP/DOWN 5

6 M456B TOGGLE FLIPFLOP PARALLEL IN P T FLIPFLOP FUNTIONAL TRUTH TABLE Preset Enable lock T n+ X X Parallel In 0 0 n 0 n 0 X n X = Don t are ARRY IN OR UP/DOWN t su 50% t h t rem f cl V SS t w(h) 50% t w(h) V SS P ENABLE V SS 0 OR ARRY OUT 90% % ARRY OUT ONLY 90% % t TLH V OH V OL t PHL t THL t PLH t PLH t rem 50% V SS t w Figure 2. Switching Time Waveforms PIN DESRIPTIONS INPUTS P0, P, P2, P3, Preset Inputs (Pi 4, 2, 3, 3) Data on these inputs is loaded into the counter when is taken high. arry In, (Pin 5) This activelow input is used when ascading stages. arry In is usually connected to arry Out of the previous stage. While high, lock is inhibited. lock, (Pin ) Binary data is incremented or decremented, depending on the direction of count, on the positive traition of this input. OUTPUTS 0,, 2, 3, Binary outputs (Pi 6,, 4, 2) Binary data is present on these outputs with 0 corresponding to the least significant bit. arry Out, (Pin 7) Used when cascading stages, arry Out is usually connected to arry In of the next stage. This synchronous output is active low and may also be used to indicate terminal count. ONTROLS, Preset Enable, (Pin ) Asynchronously loads data on the Preset Inputs. This pin is active high and inhibits the clock when high. R, Reset, (Pin 9) Asynchronously resets the out puts to a low state. This pin is active high and inhibits the clock when high. Up/Down, (Pin ) ontrols the direction of count, high for up count, low for down count. SUPPLY PINS V SS, Negative Supply Voltage, (Pin 8) This pin is usually connected to ground., Positive Supply Voltage, (Pin 6) This pin is connected to a positive supply voltage ranging from 3.0 V to 8 V. 6

7 M456B 0 = OUNT = P = UP 0 = DOWN P ENABLE in out U/D R L.S.D. M456B P0 P P2 P in out U/D R M.S.D. M456B P0 P P2 P3 TERMINAL OUNT INDIATOR P0 P P2 P3 P4 P5 P6 P7 + THUMBWHEEL SWITHES (ON FOR 0") RESISTORS = k + + ON = OUNT NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable () goes low. The Most Significant Digit (M.S.D.) is disabled while in is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches (count up mode), out goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count. (See Timing Diagram) The L.S.D. now counts through another cycle ( clock pulses) and the above cycle is repeated. Figure 3. Presettable ascaded 8Bit Up/Down ounter 7

8 M456B TIMING DIAGRAM FOR THE PTABLE ASADED 8BIT UP/DOWN OUNTER UP/DOWN ARRY IN (MSD) P7 P6 P5 P4 P3 P2 P P0 ARRY OUT (MSD) ARRY OUT (LSD) OUNT P ENABLE P ENABLE UP OUNT DOWN OUNT UP OUNT DOWN OUNT UP OUNT 8

9 M456B f out BUFFER in out U/D R L.S.D. M456B P0 P P2 P in out U/D R M.S.D. M456B P0 P P2 P3 P0 P P2 P3 P4 P5 P6 P7 (f in ) + ON = OUNT + THUMBWHEEL SWITHES (ON FOR 0") + RESISTORS = k f f out = in n NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example, the maximum divide ratio of 255 may be obtained by applying a to the preset inputs P0 to P7. For this divide operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided. Figure 4. Programmable ascaded Frequency Divider 9

10 M456B PAKAGE DIMENSIONS PDIP6 ASE ISSUE T A B NOTES:. DIMENSIONING AND TOLERANING R ANSI Y4.5M, ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MOLD FLASH. 5. ROUNDED ORNERS OPTIONAL. H G F D 6 PL S K 0.25 (0.0) M T SEATING T PLANE A M J L M INHES MILLIMETERS DIM MIN MAX MIN MAX A B D F G 0.0 BS 2.54 BS H 0 BS.27 BS J K L M 0 0 S SOEIAJ6 ASE 9660 ISSUE A e 6 9 Z b D A H E A 0.3 (0.005) M 0. (0.004) 8 E VIEW P M L E L DETAIL P c NOTES:. DIMENSIONING AND TOLERANING R ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXEED 0. (0.006) R SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL ONDITION. DAMBAR ANNOT BE LOATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPAE BETWEEN PROTRUSIONS AND ADJAENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INHES DIM MIN MAX MIN MAX A A b c D E e.27 BS 0 BS H E L L E M Z

11 M456B PAKAGE DIMENSIONS SOI6 ASE 75B05 ISSUE K A B P 8 PL 0.25 (0.0) M B S NOTES:. DIMENSIONING AND TOLERANING R ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) R SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G.27 BS 0 BS J K M P R T SEATING PLANE G D 6 PL 0.25 (0.0) M T B S A S K M R X 45 J F SOLDERING FOOTPRINT 8X X.2 6 6X PITH 8 9 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@oemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative M456B/D

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