MC74HC374A. Octal 3-State Non-Inverting D Flip-Flop. High Performance Silicon Gate CMOS

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1 M74H374A Octal 3-State Non-Inverting Flip-Flop High Performance Silicon Gate MOS The M74H374A is identical in pinout to the LS374. The device inputs are compatible with standard MOS outputs; with pullup resistors, they are compatible with LSTTL outputs. ata meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip flops, but when Output Enable is high, the outputs are forced to the high impedance state; thus, data may be stored even when the outputs are not enabled. The H374A is identical in function to the H574A which has the input pi on the opposite side of the package from the output. This device is similar in function to the H534A which has inverting outputs. PIP N SUFFIX ASE 738 MARKING IAGRAMS M74H374AN AWLYYWWG Features Output rive apability: 5 LSTTL Loads Outputs irectly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent:.0 A High Noise Immunity haracteristic of MOS evices In ompliance with the Requirements efined by JEE Standard No. 7 A hip omplexity: 266 FETs or 66.5 Equivalent Gates These evices are Pb Free and are RoHS ompliant NL Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE 00 ualified and PPAP apable SOI W SUFFIX ASE 75 TSSOP T SUFFIX ASE 948E 74H374A AWLYYWWG H 374A ALYW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. Semiconductor omponents Industries, LL, 3 June, 3 Rev. 3 Publication Order Number: M74H374A/

2 M74H374A PIN ASSIGNMENT ATA INPUTS LOK LOGI IAGRAM NONINERTING OUTPUTS OUTPUT ENABLE GN FUNTION TABLE LOK OUTPUT ENABLE PIN = PIN 0 = GN Inputs Output Output Enable lock L H H L L L L L,H, X No hange H X X Z X = don t care Z = high impedance ORERING INFORMATION M74H374ANG evice Package Shipping PIP 8 Units / Box M74H374AWG NL74H374AWG* M74H374AWR2G NL74H374AWR2G* M74H374ATG SOI WIE SOI WIE TSSOP 38 Units / Rail 000 Tape & Reel 75 Units / Rail M74H374ATR2G NL74H374ATR2G* M74H374AFG TSSOP SOEIAJ 2500 Tape & Reel 40 Units / Rail For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR80/. *NL Prefix for Automotive and Other Applicatio Requiring Unique Site and ontrol hange Requirements; AE 00 ualified and PPAP apable. 2

3 M74H374A MAXIMUM RATINGS Symbol Parameter alue Unit Supply oltage (Referenced to GN) 0.5 to in Input oltage (Referenced to GN) 0.5 to out Output oltage (Referenced to GN) 0.5 to I in Input urrent, per Pin ± ma I out Output urrent, per Pin ± 35 ma I Supply urrent, and GN Pi ± 75 ma P Power issipation in Still Air, Plastic IP SOI Package TSSOP Package T stg Storage Temperature 65 to + 50 T L Lead Temperature, mm from ase for 0 Seconds (Plastic IP, SOI, SSOP or TSSOP Package) 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditio is not implied. Extended exposure to stresses above the Recommended Operating onditio may affect device reliability. erating Plastic IP: 0 mw/ from 65 to 25 SOI Package: 7 mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 REOMMENE OPERATING ONITIONS Symbol Parameter Min Max Unit Supply oltage (Referenced to GN) in, out Input oltage, Output oltage (Referenced to GN) 0 T A Operating Temperature, All Package Types t r, t f Input Rise and Fall Time = (Figure ) = = mw This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GN ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. ELETRIAL HARATERISTIS (oltages Referenced to GN) Symbol Parameter Test onditio IH Minimum High Level Input oltage out = 0. or 0. I out A IL Maximum Low Level Input oltage out = 0. or 0. I out A OH OL Minimum High Level Output oltage Maximum Low Level Output oltage in = IH or IL I out A in = IH or IL in = IH or IL I out A in = IH or IL I out 2.4 ma I out ma I out 7.8 ma I out 2.4 ma I out ma I out 7.8 ma Guaranteed Limit 55 to I in Maximum Input Leakage urrent in = or GN ± 0. ±.0 ±.0 A Unit 3

4 M74H374A ELETRIAL HARATERISTIS (oltages Referenced to GN) Symbol I OZ I Parameter Maximum Three State Leakage urrent Maximum uiescent Supply urrent (per Package) Test onditio Output in High Impedance State in = IL or IH out = or GN in = or GN I out = 0 A 55 to 25 Guaranteed Limit Unit ± 0.5 ± ± 0 A A A ELETRIAL HARATERISTIS ( L = 50 pf, Input t r = t f = ) Symbol Parameter f max Maximum lock Frequency ( uty ycle) t PLH t PHL t PLZ t PHZ t PZL t PZH t TLH t THL Maximum Propagation elay, Input lock to (Figures and 5) Maximum Propagation elay, Output Enable to (Figures 3 and 6) Maximum Propagation elay, Output Enable to (Figures 3 and 6) Maximum Output Traition Time, Any Output (Figures and 5) Guaranteed Limit 55 to in Maximum Input apacitance pf out Maximum Three State Output apacitance (Output in High Impedance State) Unit MHz pf 25, = P Power issipation apacitance (Per Enabled Output)* * Used to determine the no load dynamic power coumption: P = P 2 f + I. 34 pf 4

5 M74H374A TIMING REUIREMENTS ( L = 50 pf, Input t r = t f = ) Symbol Parameter Figure olts t su Minimum Setup Time, ata to lock 3 t h Minimum Hold Time, lock to ata 3 t w Minimum Pulse Width, lock t r, t f Maximum Input Rise and Fall Times Guaranteed Limit 55 to Min Max Min Max Min Max Unit SWITHING WAEFORMS LOK 90% 0% 90% 0% t r t f t W t PLH t TLH /f max t PHL t THL GN OUTPUT ENABLE t PZH t PHZ t PZL t PLZ 0% 90% GN HIGH IMPEANE OL OH HIGH IMPEANE Figure. Figure 2. ALI ATA GN t su t h LOK GN Figure 3. 5

6 M74H374A TEST IRUITS TEST POINT TEST POINT EIE UNER TEST OUTPUT L * EIE UNER TEST OUTPUT k L * ONNET TO WHEN TESTING t PLZ AN t PZL. ONNET TO GN WHEN TESTING t PHZ AN t PZH. *Includes all probe and jig capacitance Figure 4. *Includes all probe and jig capacitance Figure lock Output Enable Figure 6. Expanded Logic iagram 6

7 M74H374A PAKAGE IMENSIONS PIP N SUFFIX PLASTI IP PAKAGE ASE ISSUE E A 0 B NOTES:. IMENSIONING AN TOLERANING PER ANSI YM, ONTROLLING IMENSION: INH. 3. IMENSION L TO ENTER OF LEA WHEN FORME PARALLEL. 4. IMENSION B OES NOT INLUE MOL FLASH. T SEATING PLANE G E F PL N K 0.25 (0.00) M T A M L M J PL 0.25 (0.00) M T B M INHES MILLIMETERS IM MIN MAX MIN MAX A B E BS.27 BS F G 0.00 BS 2.54 BS J K L BS 7.62 BS M N SOI W SUFFIX ASE ISSUE G H 0X 0.25 M B M E A h X 45 NOTES:. IMENSIONS ARE IN MILLIMETERS. 2. INTERPRET IMENSIONS AN TOLERANES PER ASME YM, IMENSIONS AN E O NOT INLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 PER SIE. 5. IMENSION B OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXESS OF B IMENSION AT MAXIMUM MATERIAL ONITION. X B 0.25 M T A S 8X e 0 B B S A A T SEATING PLANE L MILLIMETERS IM MIN MAX A A B E e.27 BS H h L

8 M74H374A PAKAGE IMENSIONS TSSOP T SUFFIX ASE 948E 02 ISSUE 0.5 (0.006) T L 0.5 (0.006) T U 2X L/2 PIN IENT U S S 0.00 (0.004) T SEATING PLANE X K REF 0.0 (0.004) M T U S S 0 A G H B U N J J N K K ÍÍÍÍ ÍÍÍÍ SOLERING FOOTPRINT 7.06 SETION N N 0.25 (0.00) M NOTES:. IMENSIONING AN TOLERANING PER ANSI YM, ONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXESS OF THE K IMENSION AT MAXIMUM MATERIAL ONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. F MILLIMETERS INHES IM MIN MAX MIN MAX ETAIL E A B W F G 0.65 BS BS H J ETAIL E J K K L 6.40 BS BS M PITH 6X X.26 IMENSIONS: MILLIMETERS 8

9 M74H374A ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at Marking.pdf. SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution enter for ON Semiconductor P.O. Box 563, enver, olorado 8027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@oemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative M74H374A/

10 Mouser Electronics Authorized istributor lick to iew Pricing, Inventory, elivery & Lifecycle Information: ON Semiconductor: M74H374AT M74H374ATR2 M74H374AW M74H374AWR2 M74H374AF M74H374AFEL M74H374AFELG M74H374AN M74H374ANG