MC74HC373A. Octal 3 State Non Inverting Transparent Latch. High Performance Silicon Gate CMOS

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1 Octal 3 State Non Inverting Transparent Latch High Performance Silicon Gate CMOS The MC74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high impedance state. Thus, data may be latched even when the outputs are not enabled. The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC373A is the non inverting version of the HC533A. Features Output rive Capability: 5 LSTTL Loads Outputs irectly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current:.0 A High Noise Immunity Characteristic of CMOS evices In Compliance with the JEEC Standard No. 7.0 A Requirements Chip Complexity: 86 FETs or 46.5 Equivalent Gates Pb Free Packages are Available* PIP N SUFFIX CASE 738 SOIC W SUFFIX CASE 75 TSSOP T SUFFIX CASE 948E MARKING IAGRAMS MC74HC373AN AWLYYWWG 74HC373A AWLYYWWG HC 373A ALYW SOEIAJ F SUFFIX CASE HC373A AWLYWWG A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb Free Package = Pb Free Package (Note: Microdot may be in either location) ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SORRM/. Semiconductor Components Industries, LLC, 05 July, 05 Rev. 2 Publication Order Number: MC74HC373A/

2 PIN ASSIGNMENT LOGIC IAGRAM OUTPUT ENAB ATA INPUTS NONINVERTING OUTPUTS GN LATCH ENAB LATCH ENAB OUTPUT ENAB PIN = PIN 0 = GN FUNCTION TAB Inputs Output Output Latch Enable Enable L H H H L H L L L L X No Change H X X Z X = on t Care Z = High Impedance esign Criteria Value Units Internal Gate Count* 46.5 ea Internal Gate Propagation elay.5 ns Internal Gate Power issipation 5.0 W Speed Power Product pj *Equivalent to a two input NAN gate. 2

3 MAXIMUM RATINGS Symbol Parameter Î Value Unit C Supply Voltage (Referenced to GN) Î 0.5 to V V in C Input Voltage (Referenced to GN) Î 0.5 to V V out C Output Voltage (Referenced to GN) Î 0.5 to V I in C Input Current, per Pin ± ma I out C Output Current, per Pin ± 35 ma I CC C Supply Current, and GN Pins ± 75 ma P Power issipation in Still Air, Plastic IP 750 mw SOIC Package Î 500 Î TSSOP Package Î 450 T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds C Î (Plastic IP, SOIC, SSOP or TSSOP Package) 260 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. erating Plastic IP: 0 mw/ C from 65 to 25 C SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS ata Book (L29/). RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max Unit C Supply Voltage (Referenced to GN) V V in, V out C Input Voltage, Output Voltage (Referenced to GN) 0 V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time V CC = 2.0 V ns (Figure ) = 4.5 V Î = 6.0 V ORERING INFORMATION This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GN (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. evice Package Shipping MC74HC373AN PIP 8 Units / Box MC74HC373ANG PIP (Pb Free) 8 Units / Box MC74HC373AW SOIC WIE 38 Units / Rail MC74HC373AWG SOIC WIE 38 Units / Rail (Pb Free) MC74HC373AWR2 SOIC WIE 000 Units / Reel MC74HC373AWR2G SOIC WIE 000 Units / Reel (Pb Free) MC74HC373AT TSSOP * 75 Units / Rail MC74HC373ATG TSSOP * 75 Units / Rail MC74HC373ATR2 TSSOP * 2500 Units / Reel MC74HC373ATR2G TSSOP * 2500 Units / Reel MC74HC373AF SOEIAJ 40 Units / Rail MC74HC373AFG SOEIAJ (Pb Free) 40 Units / Rail MC74HC373AFEL SOEIAJ 00 Units / Reel MC74HC373AFELG SOEIAJ (Pb Free) 00 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/. *This package is inherently Pb Free. 3

4 C ECTRICAL CHARACTERISTICS (Voltages Referenced to GN) Guaranteed Limit Î Symbol Parameter Test Conditions V 55 to 25 C 85 C 25 C Unit V IH Î Minimum High Level Input Î V out = 0. V 2.0Î V Voltage Î I out A 3.0Î Î V IL Î Maximum Low Level Input Î V out = 0. V 2.0Î V Voltage I out A Î Î V OH Minimum High Level Output V Î Voltage Î in = V IH V I out A 4.5Î Î V in = V IH I out 2.4 ma I out 6.0 ma 4.5Î I out 7.8 ma 6.0Î V OL Maximum Low Level Output V Î Î in = V IL V Voltage I out A Î V in = V IL I out 2.4 ma I out 6.0 ma I out 7.8 ma 6.0Î I in Î Maximum Input Leakage Current Î V in = or GN 6.0 Î ± 0. ±.0 ±.0 A I OZ Maximum Three State Output in High Impedance State Î Leakage Current Î V in = V IL or V IH 6.0 V out = or GN Î ± 0.5 ± 5.0 ± 0 A I CC Î Maximum uiescent Supply V Î in = or GN A Current (per Package) I out = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS ata Book (L29/). AC ECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6.0 ns) Guaranteed Limit Symbol Parameter V 55 to 25 C 85 C 25 C Unit t PLH Maximum Propagation elay, Input to ns t PHL Î (Figures and 5) 3.0Î Î t PLH Î Maximum Propagation elay, Latch Enable to 2.0Î ns t PHL (Figures 2 and 5) Î t PLZ Î Maximum Propagation elay, Output Enable to 2.0Î ns t PHZ (Figures 3 and 6) Î Î t PZL Maximum Propagation elay, Output Enable to ns t PZH Î (Figures 3 and 6) 3.0Î Î t TLH Î Maximum Output Transition Time, Any Output 2.0Î ns t THL Î (Figures and 5) 3.0Î Î C in Î Maximum Input Capacitance pf C out Maximum Three State Output Capacitance pf (Output in High Impedance State) NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed CMOS ata Book (L29/). 25 C, = 5.0 V C P Power issipation Capacitance (Per Enabled Output)* 36 pf * Used to determine the no load dynamic power consumption: P = C P V 2 CC f + I CC. For load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS ata Book (L29/). 4

5 Î TIMING REUIREMENTS (C L = 50 pf, Input t r = t f = 6.0 ns) Guaranteed Limit SymbolÎ Parameter Figure V 55 to 25 CÎ 85 C 25 C CC Volts Min Max Min Max Min Max Unit t su Î Minimum Setup Time, Input to Latch Enable Î ns Î t h Î Minimum Hold Time, Latch Enable to Input Î 5.0 ns Î Î 5.0 t w Î Minimum Pulse Width, Latch Enable Î ns Î Î 3 5 t r, t f Î Maximum Input Rise and Fall Times 2.0Î 000Î 000 ns Î 500Î Î SWITCHING WAVEFORMS INPUT t r t PLH t TLH 0% 90% 0% 90% t f GN t PHL t THL LATCH ENAB t w t PLH t PHL GN Figure. Figure 2. OUTPUT ENAB t PZH t PHZ t PZL t PLZ 0% 90%.3 V GN HIGH IMPEANCE V OL V OH HIGH IMPEANCE INPUT LATCH ENAB t su VALI t h GN GN Figure 3. Figure 4. 5

6 TEST CIRCUITS TEST POINT TEST POINT EVICE UNER TEST OUTPUT C L * EVICE UNER TEST OUTPUT k C L * CONNECT TO WHEN TESTING t PLZ AN t PZL. CONNECT TO GN WHEN TESTING t PHZ AN t PZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Figure Figure 7. EXPANE LOGIC IAGRAM 6

7 PACKAGE IMENSIONS PIP N SUFFIX PLASTIC IP PACKAGE CASE ISSUE E A 0 B NOTES:. IMENSIONING AN TORANCING PER ANSI Y4.5M, CONTROLLING IMENSION: INCH. 3. IMENSION L TO CENTER OF A WHEN FORME PARALL. 4. IMENSION B OES NOT INCLUE MOL FLASH. T SEATING PLANE G E F N K C PL 0.25 (0.00) M T A M L M J PL 0.25 (0.00) M T B M INCHES MILLIMETERS IM MIN MAX MIN MAX A B C E BSC.27 BSC F G 0.00 BSC 2.54 BSC J K L BSC 7.62 BSC M N SOIC W SUFFIX CASE ISSUE G H 0X 0.25 M B M E A h X 45 NOTES:. IMENSIONS ARE IN MILLIMETERS. 2. INTERPRET IMENSIONS AN TORANCES PER ASME Y4.5M, IMENSIONS AN E O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 PER SIE. 5. IMENSION B OES NOT INCLUE AMBAR PROTRUSION. ALLOWAB PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF B IMENSION AT MAXIMUM MATERIAL CONITION. X B 0.25 M T A S 8X e 0 B B S A A T SEATING PLANE C L MILLIMETERS IM MIN MAX A A B C E e.27 BSC H h L

8 PACKAGE IMENSIONS TSSOP T SUFFIX CASE 948E 02 ISSUE B 0.5 (0.006) T L U 2X L/2 0.5 (0.006) T U S PIN IENT S C 0.00 (0.004) T SEATING PLANE X K REF 0.0 (0.004) M T U S V S 0 A V G H B U J J N N K K ÍÍÍÍ ÍÍÍÍ SECTION N N F ETAIL E 0.25 (0.00) ETAIL E M W NOTES:. IMENSIONING AN TORANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERA FLASH OR PROTRUSION. INTERA FLASH OR PROTRUSION SHALL NOT EXCEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWAB AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M

9 PACKAGE IMENSIONS SOEIAJ F SUFFIX CASE ISSUE O e E H E 0 Z A L E M L ETAIL P VIEW P c NOTES:. IMENSIONING AN TORANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS AN E O NOT INCLUE MOL FLASH OR PROTRUSIONS AN ARE MEASURE AT THE PARTING LINE. MOL FLASH OR PROTRUSIONS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE A WITH IMENSION (b) OES NOT INCLUE AMBAR PROTRUSION. ALLOWAB AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE A WITH IMENSION AT MAXIMUM MATERIAL CONITION. AMBAR CANNOT BE LOCATE ON THE LOWER RAIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AN AJACENT A TO BE 0.46 ( 0.08). b 0.3 (0.005) M A 0.0 (0.004) MILLIMETERS INCHES IM MIN MAX MIN MAX A A b c E e.27 BSC BSC H E L L E M Z

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