MC74LVX Bit Addressable Latch/1 of 8 Decoder CMOS Logic Level Shifter. with LSTTL Compatible Inputs

Size: px

Start display at page:

Download "MC74LVX Bit Addressable Latch/1 of 8 Decoder CMOS Logic Level Shifter. with LSTTL Compatible Inputs"

Linda Dennis
5 years ago
Views:

8Bit Addressable Latch/of8 ecoder CMOS Logic Level Shifter with LSTTLCompatible Inputs The MCLVX9 is an 8bit Addressable Latch fabricated with silicon gate CMOS technology.

1 8Bit Addressable Latch/of8 ecoder CMOS Logic Level Shifter with LSTTLCompatible Inputs The MCLVX9 is an 8bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The LVX9 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on ata In is written into the addressed latch. The addressed latch follows the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the ata or Address inputs. In the oneofeight decoding or demultiplexing mode, the addressed output follows the state of ata In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the LVX9 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MCLVX9 input structure provides protection when voltages up to.0 V are applied, regardless of the supply voltage. This allows the MCLVX9 to be used to interface.0 V circuits to.0 V circuits. Features High Speed: t P =.0 ns (Typ) at =. V Low Power issipation: I CC = A (Max) at T A = C High Noise Immunity: V NIH = V NIL = 8% CMOSCompatible Outputs: V OH > 0.8 ; V OL < Power own Protection Provided on Inputs and Outputs Balanced Propagation elays Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 00 ma ES Performance: Human Body Model > 000 V; Machine Model > 00 V PbFree Packages are Available* SOIC SUFFIX CASE B TSSOP T SUFFIX CASE 98F SOEIAJ M SUFFIX CASE 9 MARKING IAGRAMS A = Assembly Location WL or L = Wafer Lot Y = Year WW or W = Work Week ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. LVX9 AWLYWW LVX 9 ALYW LVX9 ALYW *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. Semiconductor Components Industries, LLC, 00 March, 00 Rev. Publication Order Number: MCLVX9/

2 A0 A A Q Q RESET ENABLE ATA IN Q Q ARESS INPUTS A0 A A ATA IN 9 0 Q Q Q Q Q Q Q NONINVERTING OUTPUTS Q GN Q Q RESET ENABLE PIN = PIN 8 = GN Figure. Pin Assignment Figure. Logic iagram A0 A A BIN/OCT I EN R Q Q Q Q Q Q Q A0 A A MUX 0 G 0 I EN R Q Q Q Q Q Q Q Figure. IEC Logic Symbol MOE SELECTION TABLE LATCH SELECTION TABLE Enable Reset Mode L H Addressable Latch H L H H L L Memory 8Line emultiplexer Reset Address Inputs C B A L L L L L H L H L L H H H L L H L H H H L H H H Latch Addressed Q Q Q Q Q Q Q

3 ATA INPUT Q Q Q A0 ARESS INPUTS A TO 8 ECOER A 9 Q 0 Q ENABLE Q Q RESET Figure. Expanded Logic iagram

4 MAXIMUM RATINGS Symbol Parameter Value Unit Positive C Supply Voltage 0. to +.0 V V IN igital Input Voltage 0. to +.0 V V OUT C Output Voltage 0. to +0. V I IK Input iode Current 0 ma I OK Output iode Current 0 ma I OUT C Output Current, per Pin ma I CC C Supply Current, and GN Pins ma P Power issipation in Still Air SOIC Package TSSOP T STG Storage Temperature Range to +0 C V ES ES Withstand Voltage Human Body Model (Note ) Machine Model (Note ) Charged evice Model (Note ) >000 >00 >000 I LATCHUP Latchup Performance Above and Below GN at C (Note ) 00 ma JA Thermal Resistance, JunctiontoAmbient SOIC Package TSSOP Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Tested to EIA/JESAA. Tested to EIA/JESAA. Tested to JESC0A. Tested to EIA/JES8 RECOMMENE OPERATING CONITIONS Symbol Characteristics Min Max Unit C Supply Voltage.0. V V IN C Input Voltage 0. V V OUT C Output Voltage 0 V T A Operating Temperature Range, all Package Types 0 8 C t r, t f Input Rise or Fall Time =. V + 0. V 0 00 ns/v mw V C/W

5 C CHARACTERISTICS (Voltages Referenced to GN) T A = C 0 C T A 8 C Symbol Parameter Condition (V) Min Typ Max Min Max Unit V IH V IL V OH V OL Minimum HighLevel Input Voltage Maximum LowLevel Input Voltage HighLevel Output Voltage LowLevel Output Voltage I OH = 0 A V I OH = 0 A I OH = ma I OL = 0 A V I OL = 0 A I OL = ma I IN Input Leakage Current V IN =. V or GN 0 to. ±0. ±.0 A I CC Maximum Quiescent Supply Current (per package) V IN = or GN A AC ELECTRICAL CHARACTERISTICS Input t r = t f =.0 ns ÎÎ T A = C 0 C T A 8 C Î Î Î Symbol Parameter Test Conditions Min Typ Max Min Max Unit Î t PLH Î, Maximum Propagation =. V C L Î = pf Î Î elay, ata to Output Î C L = 0pF Î ns Î Î (Figures and 9) Î =. V ± 0. V C L = pf.î 8.0.0Î.0 C L = 0pF Î Î Î t Î PLH, Maximum Propagation V Î elay, Address Select Î CC =. V C L = pf C L ns = 0pF Î Î Î to Output Î (Figures and 9) =. V ± 0. V C L Î = pf Î C L = 0pF Î Î.0 Î t PLH, Î Maximum PropagationÎ =. V C L = pf t Î PHL elay, Enable to Output C Î Î L = 0pF. Î Î ns (Figures and 9) V Î Î CC =. V ± 0. V C L = pf.î 9.0.0Î.0 C L = 0pF Î t Î PHL Maximum Propogation V Î elay, Reset to OutputÎ CC =. V C L = pf C L = 0pF Î Î.0 ns Î Î Î (Figures and 9) Î =. V ± 0. V C L = pf C Î L = 0pF Î C IN Î Maximum Input Î 0 Î 0 pf Capacitance C, =. V C P Power issipation Capacitance (Note ) 0 pf. C P is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C P f in + I CC. C P is used to determine the noload dynamic power consumption; P = C P V CC f in + I CC. V V

6 TIMING REQUIREMENTS Input t r = t f =.0 ns T A = C ÎÎ T A = 8 C SymbolÎ Parameter Test Conditions Min Typ Max Min Max Unit Î t w Î Minimum Pulse Width, Reset or Enable =. V..0 ns (Figure 8) =. V ± 0. V..0 Î t su Î Minimum Setup Time, Address or ata to Enable =. V.0.0 ns (Figure 8) =. V ± 0. V.0.0 Î t h Î Minimum Hold Time, Enable to Address or ata =. V.0.0 ns (Figure or 8) =. V ± 0. V.0.0 Î t r, t f Î Maximum Input, Rise and Fall Times =. V ns (Figure ) =. V ± 0. V t r ATA IN OUTPUT Q t PLH t f GN ATA IN ARESS SELECT OUTPUT Q GN GN GN Figure. Switching Waveform Figure. Switching Waveform ATA IN GN ATA IN GN ENABLE OUTPUT Q t w t w GN RESET OUTPUT Q t w GN Figure. Switching Waveform Figure 8. Switching Waveform ATA IN OR ARESS SELECT ENABLE t su t h(h) th(h) t su Figure 9. Switching Waveform GN GN EVICE UNER TEST OUTPUT TEST POINT C L * *Includes all probe and jig capacitance Figure 0. Test Circuit

7 ORERING INFORMATION evice Package Shipping MCLVX9 SOIC 8 Units / Rail MCLVX9G SOIC (PbFree) 8 Units / Rail MCLVX9R SOIC 00 Tape & Reel MCLVX9RG SOIC (PbFree) 00 Tape & Reel MCLVX9T TSSOP* 9 Units / Rail MCLVX9TR TSSOP* 00 Tape & Reel MCLVX9M SOEIAJ 0 Units / Rail MCLVX9MG SOEIAJ (PbFree) 0 Units / Rail MCLVX9MEL SOEIAJ 000 Tape & Reel MCLVX9MELG SOEIAJ (PbFree) 000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/. *This package is inherently PbFree. EMBOSSE CARRIER IMENSIONS (See Notes and ) Tape Size B Max E F K P P 0 P R T W 8 mm. mm (0.9 ) mm 8. mm (0. ). mm ( ).0 mm Min (0.9 ). mm Min (0.00). mm ±0. (0.09 ). mm ±0. (.8 ±0.00 ). mm ±0. (0. ±0.00 ). mm Max (0.09 ). mm Max (0. ).0 mm ±0.0 (0..0 mm ±0.0 ( mm ±0.0 (0..0 mm ±0. (0..0 mm ±0. (0.09 ) ) mm (0.98 ) 0 mm (.8 ) 0. mm (0.0) 8. mm (0.).0 mm ±0. (0.0 ±0.0 ) mm. mm (0. ). mm ±0.0 (0.9.9 mm Max (0. ).0 mm ±0.0 ( mm ±0.0 (0..0 mm ±0.0 (0.. mm (0.) mm 0. mm (0.9 ). mm ±0.0 (0..9 mm Max (0.8 ).0 mm ±0.0 (0.. mm (0.9). Metric imensions GovernEnglish are in parentheses for reference only.. A 0, B 0, and K 0 are determined by component size. The clearance between the components and the cavity must be within 0.0 mm min to 0.0 mm max. The component cannot rotate more than 0 within the determined cavity

8 PACKAGE IMENSIONS SOIC SUFFIX CASE B0 ISSUE J A 9 8 B P 8 PL 0. (0.00) M B S NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y.M, 98.. CONTROLLING IMENSION: MILLIMETER.. IMENSIONS A AN B O NOT INCLUE MOL PROTRUSION.. MAXIMUM MOL PROTRUSION 0. (0.00) PER SIE.. IMENSION OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0. (0.00) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION. T SEATING PLANE G K C PL 0. (0.00) M T B S A S M R X J F MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G. BSC 0.00 BSC J K M 0 0 P R TSSOP T SUFFIX CASE 98F0 ISSUE A 0. (0.00) T 0. (0.00) T 0.0 (0.00) T SEATING PLANE L U PIN IENT. U S S X L/ C X K REF 0.0 (0.00) M T U S V S 9 8 A V G B U N H N J J F ETAIL E ETAIL E K K ÇÇÇ ÉÉÉ SECTION NN 0. (0.00) M W NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y.M, 98.. CONTROLLING IMENSION: MILLIMETER.. IMENSION A OES NOT INCLUE MOL FLASH. PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0. (0.00) PER SIE.. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0. (0.00) PER SIE.. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.00) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION.. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0. BSC 0.0 BSC H J J K K L.0 BSC 0. BSC M

9 SOEIAJ M SUFFIX CASE 90 ISSUE O e 9 Z b A H E A 0. (0.00) M 0.0 (0.00) 8 E VIEW P M L E Q L ETAIL P c NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y.M, 98.. CONTROLLING IMENSION: MILLIMETER.. IMENSIONS AN E O NOT INCLUE MOL FLASH OR PROTRUSIONS AN ARE MEASURE AT THE PARTING LINE. MOL FLASH OR PROTRUSIONS SHALL NOT EXCEE 0. (0.00) PER SIE.. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. THE LEA WITH IMENSION (b) OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.00) TOTAL IN EXCESS OF THE LEA WITH IMENSION AT MAXIMUM MATERIAL CONITION. AMBAR CANNOT BE LOCATE ON THE LOWER RAIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AN AJACENT LEA TO BE 0. ( 0.08). MILLIMETERS INCHES IM MIN MAX MIN MAX A A b c E e. BSC 0.00 BSC H E L L E M Q Z

10 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box, Phoenix, Arizona 808 USA Phone: or Toll Free USA/Canada Fax: or 8008 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguroku, Tokyo, Japan 00 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. MCLVX9/

with LSTTL Compatible Inputs

with LSTTL Compatible Inputs The MCLVX9 is an 8 bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides