with LSTTL Compatible Inputs

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1 with LSTTL Compatible Inputs The MCLVX9 is an 8 bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The LVX9 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table.. In the addressable latch mode, the data on ata In is written into the addressed latch. The addressed latch follows the data input with all non addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the ata or Address inputs. In the one of eight decoding or demultiplexing mode, the addressed output follows the state of ata In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the LVX9 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MCLVX9 input structure provides protection when voltages up to V are applied, regardless of the supply voltage. This allows the MCLVX9 to be used to interface V circuits to V circuits. High Speed: t P =.0 ns (Typ) at =. V Low Power issipation: I CC = µa (Max) at T A = C High Noise Immunity: V NIH = V NIL = 8% CMOS Compatible Outputs: V OH > 0.8 ; V OL < Power own Protection Provided on Inputs and Outputs Balanced Propagation elays Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 00 ma ES Performance: HBM > 000 V; Machine Model > 00 V SOIC SUFFIX CASE B TSSOP T SUFFIX CASE 98F SOIC EIAJ M SUFFIX CASE 9 MARKING IAGRAMS LVX9 AWLYYWW LVX 9 AWLYWW LVX9 ALYW A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORERING INFORMATION evice Package Shipping MCLVX9 SO 8 Units/Rail MCLVX9R SO 00 Units/Reel MCLVX9T TSSOP 9 Units/Rail MCLVX9TR TSSOP 000 Units/Reel MCLVX9M SO EIAJ 8 Units/Rail MCLVX9MEL SO EIAJ 000 Units/Reel Semiconductor Components Industries, LLC, 00 April, 00 Rev. Publication Order Number: MCLVX9/

2 A0 A A Q Q RESET ENABLE ATA IN Q Q ARESS INPUTS A0 A A ATA IN 9 0 Q Q Q Q Q Q Q NONINVERTING OUTPUTS Q GN Q Q RESET ENABLE PIN = PIN 8 = GN Figure. Pin Assignment Figure. Logic iagram A0 A A I EN R Q Q Q Q Q Q Q A0 A A 0 G 0 I EN R Q Q Q Q Q Q Q Figure. IEC Logic Symbol MOE SELECTION TABLE LATCH SELECTION TABLE Enable Reset Mode L H Addressable Latch H L H H L L Memory 8 Line emultiplexer Reset Address Inputs C B A L L L L L H L H L L H H H L L H L H H H L H H H Latch Addressed Q Q Q Q Q Q Q

3 ATA INPUT Q Q Q A0 ARESS INPUTS A TO 8 ECOER A 9 Q 0 Q ENABLE Q Q RESET Figure. Expanded Logic iagram

4 MAXIMUM RATINGS (Note.) Symbol Parameter Value Unit Positive C Supply Voltage 0. to +.0 V V IN igital Input Voltage 0. to +.0 V V OUT C Output Voltage 0. to +0. V I IK Input iode Current 0 ma I OK Output iode Current 0 ma I OUT C Output Current, per Pin ma I CC C Supply Current, and GN Pins ma P Power issipation in Still Air SOIC Package TSSOP T STG Storage Temperature Range to +0 C V ES ES Withstand Voltage Human Body Model (Note.) Machine Model (Note.) Charged evice Model (Note.) >000 >00 >000 I LATCH UP Latch Up Performance Above and Below GN at C (Note.) 00 ma JA Thermal Resistance, Junction to Ambient SOIC Package TSSOP. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.. Tested to EIA/JES A A. Tested to EIA/JES A A. Tested to JES C0 A. Tested to EIA/JES8 mw V C/W RECOMMENE OPERATING CONITIONS Symbol Characteristics Min Max Unit C Supply Voltage.0. V V IN C Input Voltage 0. V V OUT C Output Voltage 0 V T A Operating Temperature Range, all Package Types 0 8 C t r, t f Input Rise or Fall Time =. V + 0. V 0 00 ns/v

5 C CHARACTERISTICS (Voltages Referenced to GN) T A = C 0 C T A 8 C Symbol Parameter Condition (V) Min Typ Max Min Max Unit V IH V IL V OH V OL Minimum High Level Input Voltage Maximum Low Level Input Voltage High Level Output Vlt Voltage Low Level Output Vlt Voltage I OH = 0 µa V I OH = 0 µa I OH = ma I OL = 0 µa V I OL = 0 µa I OL = ma I IN Input Leakage Current V IN =. V or GN 0 to. ±0. ±.0 µa I CC Maximum Quiescent Supply Current (per package) V IN = or GN µa Î AC ELECTRICAL CHARACTERISTICS Input t r = t f =.0 ns T A ÎÎ ÎÎ = C 0 C T A 8 C Î Symbol Parameter Test Conditions Min Typ Max Min Max Unit t PLH Î Î, Maximum Propagation elay, =. V C L = pf Î ata to Output Î C L = 0pF ÎÎ ns Î (Figures and 9) Î =. V ± 0. V C L = pf C L = 0pF ÎÎ.0.0 ÎÎ t PLH, Maximum Propagation elay, V Î Î CC =. V C L = pf Address Select to Output C L Î ns = 0pF Î (Figures and 9) Î =. V ± 0. V C L = pf Î Î C L = 0pF ÎÎ t PLH, Î Maximum Propagation elay, Î =. V C L = pf t PHL Enable to Output C Î Î L = 0pF. 9.0 ÎÎ ÎÎ.0.0 Î ns (Figures NO TAG and 9) =. V ± 0. V C L = pf ÎÎ ÎÎ C L = 0pF ÎÎ t PHL Maximum Propogation elay, V Î Reset to Output Î CC =. V C L = pf C L = 0pF ÎÎ ns Î (Figures and 9) Î =. V ± 0. V C L = pf Î Î C L = 0pF. 9.0 ÎÎ ÎÎ.0.0 ÎÎ C IN Î Maximum Input Capacitance ÎÎ 0 ÎÎ 0 ÎÎ pf C, =. V C P Power issipation Capacitance (Note.) 0 pf. C P is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C P f in + I CC. C P is used to determine the no load dynamic power consumption; P = C P V CC f in + I CC. V V

6 TIMING REQUIREMENTS Input t r = t f =.0 ns T A = C Î T A = 8 C SymbolÎÎ Parameter Î Test Conditions Min Typ Max Min Max Unit t w ÎÎ Minimum Pulse Width, Î =. V..0Î ns Reset or Enable Î (Figure 8) Î =. V ± 0. V..0 Î t su ÎÎ Minimum Setup Time, =. V.0.0 Î ns Î Address or ata to Enable (Figure 8) =. V ± 0. V.0.0 Î Î t h Minimum Hold Time, =. V.0.0 ns ÎÎ Enable to Address or ata Î ÎÎ (Figure or 8) V Î CC =. V ± 0. V.0.0 t r, t f ÎÎ Maximum Input, Î =. V 00 Î 00 ns Rise and Fall Times Î (Figure ) Î =. V ± 0. V 00Î 00 t r ATA IN OUTPUT Q t PLH t f GN ATA IN ARESS SELECT OUTPUT Q GN GN GN Figure. Switching Waveform Figure. Switching Waveform ATA IN GN ATA IN GN ENABLE OUTPUT Q t w t w GN RESET OUTPUT Q t w GN Figure. Switching Waveform Figure 8. Switching Waveform ATA IN OR ARESS SELECT ENABLE t su t h(h) th(h) t su Figure 9. Switching Waveform GN GN EVICE UNER TEST OUTPUT TEST POINT C L * *Includes all probe and jig capacitance Figure 0. Test Circuit

7 K t TOP COVER TAPE P P 0 0 PITCHES CUMULATIVE TOLERANCE ON TAPE ±0. mm (±0.008 ) E B K 0 SEE NOTE. FOR MACHINE REFERENCE ONLY INCLUING RAFT AN RAII CONCENTRIC AROUN B 0 A 0 B 0 SEE NOTE. EMBOSSMENT USER IRECTION OF FEE CENTER LINES OF CAVITY F W FOR COMPONENTS.0 mm. mm AN LARGER *TOP COVER TAPE THICKNESS (t ) 0.0 mm (0.00 ) MAX. R MIN. BENING RAIUS TAPE AN COMPONENTS SHALL PASS AROUN RAIUS R WITHOUT AMAGE EMBOSSE CARRIER EMBOSSMENT 0 MAXIMUM COMPONENT ROTATION 00 mm (.9 ) mm MAX TYPICAL COMPONENT CAVITY CENTER LINE TAPE TYPICAL COMPONENT CENTER LINE mm (0.09 ) MAX 0 mm (9.8 ) CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE mm/00 mm NONACCUMULATIVE OVER 0 mm. A 0, B 0, and K 0 are determined by component size. The clearance between the components and the cavity must be within 0.0 mm min to 0.0 mm max. The component cannot rotate more than 0 within the determined cavity Figure. Carrier Tape Specifications

8 EMBOSSE CARRIER IMENSIONS (See Notes 8. and 9.) Tape Size B Max E F K P P 0 P R T W 8 mm. mm (0.9 ) mm 8. mm (0. ) mm. mm (0. ) mm 0. mm (0.9 ). mm ( ).0 mm Min (0.9 ). mm Min (0.00). mm ±0. (0.09 ). mm ±0. (.8 ±0.00 ). mm ±0. (0. ±0.00 ). mm (0.9. mm (0.. mm Max (0.09 ). mm Max (0. ).9 mm Max (0. ).9 mm Max (0.8 ).0 mm (0..0 mm ( mm (0..0 mm ( mm (0..0 mm (0..0 mm (0..0 mm ±0. (0..0 mm ±0. (0.09 ) ) mm (0.98 ) 0 mm (.8 ) 0. mm (0.0) 8. mm (0.).0 mm ±0. (0.0 ±0.0 ). mm (0.). mm (0.9) 8. Metric imensions Govern English are in parentheses for reference only. 9. A 0, B 0, and K 0 are determined by component size. The clearance between the components and the cavity must be within 0.0 mm min to 0.0 mm max. The component cannot rotate more than 0 within the determined cavity 8

9 t MAX. mm MIN (0.0 ).0 mm ±0. mm (0. ±0.008 ) A 0. mm MIN (0.9 ) 0 mm MIN (.99 ) FULL RAIUS G Figure. Reel imensions REEL IMENSIONS Tape Size T&R Suffix A Max G t Max 8 mm T, T 8 mm ( ) 8 mm T, T 0 mm ( ) mm R 0 mm ( ) mm R 0 mm (. ) mm R 0 mm (. ) 8. mm, +. mm, 0.0 ( , 0.00) 8. mm, +. mm, 0.0 ( , 0.00). mm, +.0 mm, 0.0 ( , 0.00). mm, +.0 mm, 0.0 ( , 0.00). mm, +.0 mm, 0.0 ( , 0.00). mm (0. ). mm (0. ) 8. mm (0. ). mm (0.88 ) 0. mm (.9 ) IRECTION OF FEE BARCOE LABEL POCKET HOLE Figure. Reel Winding irection 9

10 CAVITY TAPE TOP TAPE TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 0 mm MIN COMPONENTS IRECTION OF FEE TAPE LEAER NO COMPONENTS 00 mm MIN Figure. Tape Ends for Finished Goods User irection of Feed Figure. TSSOP and SOIC R Reel Configuration/Orientation TAPE UTILIZATION BY PACKAGE Tape Size SOIC TSSOP QFN SC88A / SOT SC88/SOT 8 mm, Lead mm 8 Lead 8,, Lead 8,, Lead mm, Lead 0, Lead 0, Lead mm 8, 0,, 8 Lead 8, Lead 8, Lead 0

11 PACKAGE IMENSIONS T G A PL K B C SOIC SUFFIX CASE B 0 ISSUE J P 8 PL M R X J F TSSOP T SUFFIX CASE 98F 0 ISSUE O T L PIN IENT. X L/ C X K REF 9 8 A V G B U H N N J J F ETAIL E ETAIL E K K ÇÇÇ ÉÉ SECTION N N M W

MC74LVX Bit Addressable Latch/1 of 8 Decoder CMOS Logic Level Shifter. with LSTTL Compatible Inputs

MC74LVX Bit Addressable Latch/1 of 8 Decoder CMOS Logic Level Shifter. with LSTTL Compatible Inputs 8Bit Addressable Latch/of8 ecoder CMOS Logic Level Shifter with LSTTLCompatible Inputs The MCLVX9 is an 8bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed