74HC238; 74HCT to-8 line decoder/demultiplexer
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- Agatha Morris
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1 Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (0, 1, 2) and when enabled, provide 8 mutually exclusive active HIGH outputs (Y0 to Y7). The 74HC238/74HCT238 features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 238 to a 1-to-32 (5 lines to 32 lines) decoder with just four 238 ICs and one inverter. The 238 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The 74HC238/74HCT238 is similar to the 74HC138/74HCT138 but has non-inverting outputs. Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding ctive HIGH mutually exclusive outputs Multiple package options Complies with JEDEC standard no. 7 ESD protection: HBM JESD22-114E exceeds 2000 V MM JESD exceeds 200 V Specified from 40 C to+85 C and from 40 C to +125 C
2 3. Ordering information Table 1. Type number Ordering information Package Temperature range Name Description Version 74HC238N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT HC238D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm 74HC238DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 74HC238PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 4. Functional diagram SOT109-1 SOT338-1 SOT HC238BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body mm SOT HCT238N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT HCT238D 40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74HCT238DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT238PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT HCT238BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body mm SOT TO 8 DECODER 2 3 ENBLE EXITING Y0 Y1 Y2 Y3 Y4 Y5 Y TO 8 DECODER ENBLE EXITING Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 E1 E2 E Y7 001aag752 E1 E2 E aag753 Fig 1. Logic symbol Fig 2. Functional diagram Product data sheet 2 of 18
3 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V [1] - ±20 m I OK output clamping current V O < 0.5 V or V O >V CC V [1] - ±20 m I O output current 0.5 V < V O < V CC V - ±25 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature C P tot total power dissipation DIP16 package [2] mw SO16, SSOP16, TSSOP16 and DHVQFN16 packages [3] mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 packages: above 70 C the value of P tot derates linearly at 12 mw/k. [3] For SO16 packages: above 70 C the value of P tot derates linearly at 8 mw/k. For SSOP16 and TSSOP16 packages: above 60 C the value of P tot derates linearly at 5.5 mw/k. For DHVQFN16 packages: above 60 C the value of P tot derates linearly at 4.5 mw/k. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC238 74HCT238 Unit Min Typ Max Min Typ Max V CC supply voltage V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature C t/ V input transition rise V CC = 2.0 V ns/v and fall rate V CC = 4.5 V ns/v V CC = 6.0 V ns/v Product data sheet 5 of 18
4 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit 74HC238 V IH HIGH-level input voltage V IL V OH V OL I I LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current Min Typ Max Min Max Min Max V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V I =V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V I =V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V I =V CC or GND; - - ±0.1 - ±1.0 - ±1.0 µ V CC = 6.0 V µ I CC supply current V I =V CC or GND; I O =0; V CC = 6.0 V C I input capacitance 74HCT238 V IH HIGH-level input voltage V IL LOW-level input voltage V OH HIGH-level output voltage V OL I I LOW-level output voltage input leakage current pf V CC = 4.5 V to 5.5 V V V CC = 4.5 V to 5.5 V V V I =V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4.0 m V V I =V IH or V IL ; V CC = 4.5 V I O =20µ V I O = 4.0 m V V I =V CC or GND; - - ±0.1 - ±1.0 - ±1.0 µ V CC = 5.5 V Product data sheet 6 of 18
5 Table 6. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max I CC supply current V I =V CC or GND; V CC = 5.5 V; I O =0 I CC C I additional supply current input capacitance 10. Dynamic characteristics µ per input pin; V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V; I O =0 n inputs µ E1, E2 inputs µ E3 input µ pf Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +125 C Min Typ Max Max (85 C) Max (125 C) 74HC238 t pd propagation delay n to Yn; see Figure 6 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns V CC = 6.0 V ns E3 to Yn; see Figure 6 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns V CC = 6.0 V ns En to Yn or see Figure 7 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns V CC = 6.0 V ns t t transition time see Figure 6 and Figure 7 [2] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns C PD power dissipation capacitance per package; V I = GND to V CC [3] pf Unit Product data sheet 7 of 18
6 Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +125 C 74HCT238 t pd propagation delay n to Yn; see Figure 6 [1] V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns E3 to Yn; see Figure 6 [1] V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns En to Yn or see Figure 7 [1] V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns t t transition time V CC = 4.5 V; [2] ns see Figure 6 and Figure 7 C PD power dissipation capacitance per package; V I = GND to V CC 1.5 V [3] pf [1] t pd is the same as t PHL and t PLH. [2] t t is the same as t THL and t TLH. [3] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. 11. Waveforms Min Typ Max Max (85 C) Max (125 C) Unit n, E3 input V M t PHL t PLH Yn output V Y V M V X t THL t TLH 001aag757 Fig 6. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Input (n, E3) to output (Yn) propagation delays and output transition times Product data sheet 8 of 18
7 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D M E seating plane 2 L 1 Z 16 e b b 1 9 b 2 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT 1 2 (1) (1) (1) max. b 1 b 2 c D E e L M Z min. max. b e 1 M E H w max. mm inches Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION Fig 9. Package outline SOT38-4 (DIP16) Product data sheet 11 of 18
8 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E X c y H E v M Z 16 9 Q 2 1 ( ) 3 pin 1 index θ L p 1 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION SOT E07 MS-012 Fig 10. Package outline SOT109-1 (SO16) Product data sheet 12 of 18
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Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
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Rev. 1 20 November 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
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Rev. 05 5 May 2008 Product data sheet 1. General description 2. Features 3. pplications The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance
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Rev. 30 July 202 Product data sheet. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 06 20 December 2007 Product data sheet. General description 2. Features 3. pplications The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HCU04. The is a general purpose
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Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
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Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
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Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
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Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.
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Rev. 9 July 202 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
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Rev. 9 13 December 2011 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard
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Rev. 4 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device
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Rev. 7 2 pril 2013 Product data sheet 1. General description The is a quad single pole, single throw analog switch. Each switch features two input/output terminals (ny and nz) and an active HIGH enable
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