MC74LCX Low-Voltage CMOS 16-Bit Transparent Latch. With 5 V-Tolerant Inputs and Outputs (3-State, Non-Inverting)

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Low-oltage CMOS 16-Bit Traparent Latch With 5 -Tolerant Inputs and Outputs (3-State, Non-Inverting) The MC74LCX16373 is a high performance, non-inverting 16-bit traparent latch operating from a 2.

1 Low-oltage CMOS 16-Bit Traparent Latch With 5 -Tolerant Inputs and Outputs (3-State, Non-Inverting) The MC74LCX16373 is a high performance, non-inverting 16-bit traparent latch operating from a 2.3 to 3.6 supply. The device is byte controlled. Each byte has separate Output Enable and Latch Enable inputs. These control pi can be tied together for full 16-bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A I specification of 5.5 allows MC74LCX16373 inputs to be safely driven from 5.0 devices. The MC74LCX16373 contai 16 -type latches with 3-state 5.0 -tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the n inputs enters the latches. In this condition, the latches are traparent, i.e., a latch output will change state each time its input changes. When LE is LOW, the latches store the information that was present on the inputs a setup time preceding the HIGH-to-LOW traition of LE. The 3-state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. 1 TSSOP- T SUFFIX CASE 1201 MARKING IAGRAM LCX16373G AWLYYWW Features esigned for 2.3 to 3.6 Operation 5.4 Maximum t pd 5.0 Tolerant - Interface Capability With 5.0 TTL Logic Supports Live Iertion and Withdrawal I OFF Specification Guarantees High Impedance When = 0 LTTL Compatible LCMOS Compatible 24 ma Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (20 A) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 ma ES Performance: Human Body Model >2000 ; Machine Model >200 These are Pb-Free evices* 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 3 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. Semiconductor Components Industries, LLC, 2007 November, Rev. 7 1 Publication Order Number: MC74LCX16373/

2 OE1 O0 1 LE OE1 LE1 1 OE2 LE O1 GN O2 O GN O0 O O8 O9 O O5 GN O6 O7 O GN O2 O O10 O11 O9 GN O GN O O12 O O O O13 O13 GN O GN O O14 O15 OE LE O O15 Figure 1. Pinout: -Lead (Top iew) Figure 2. Logic iagram Table 1. PIN NAMES OEn LEn 0-15 O0-O15 Pi Output Enable Inputs Latch Enable Inputs Inputs Outputs Function TRUTH TABLE Inputs Outputs Inputs Outputs LE1 OE1 0:7 O0:7 LE2 OE2 8:15 O8:15 X H X Z X H X Z H L L L H L L L H L H H H L H H L L X O0 L L X O0 H = High oltage Level L = Low oltage Level Z = High Impedance State X = High or Low oltage Level and Traitio Are Acceptable; for I CC reaso, O NOT FLOAT Inputs 2

3 ORERING INFORMATION evice Package Shipping MC74LCX16373T TSSOP-* 39 Units / Rail MC74LCX16373TG TSSOP-* 39 Units / Rail MC74LCX16373TR2 TSSOP-* 2500 / Tape & Reel M74LCX16373TR2G TSSOP-* 2500 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR8011/. *This package is inherently Pb-Free. MAXIMUM RATINGS Symbol Parameter alue Condition Unit C Supply oltage -0.5 to +7.0 I C Input oltage -0.5 I +7.0 O C Output oltage -0.5 O +7.0 Output in 3-State -0.5 O Output in HIGH or LOW State. (Note 1) I IK C Input iode Current -50 I < GN ma I OK C Output iode Current -50 O < GN ma +50 O > ma I O C Output Source/Sink Current ±50 ma I CC C Supply Current Per Supply Pin ±100 ma I GN C Ground Current Per Ground Pin ±100 ma T STG Storage Temperature Range -65 to +150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. 1. I O absolute maximum rating must be observed. RECOMMENE OPERATING CONITIONS Symbol Parameter Min Typ Max Unit Supply oltage Operating ata Retention ly , , 3.3 I Input oltage O Output oltage (HIGH or LOW State) (3-State) I OH HIGH Level Output Current = = = ma I OL LOW Level Output Current = = = ma T A Operating Free-Air Temperature C t/ Input Traition Rise or Fall Rate, IN from 0.8 to 2.0, = / 3

4 C ELECTRICAL CHARACTERISTICS Symbol Characteristic Condition T A = -55 C to +125 C IH HIGH Level Input oltage (Note 2) Min IL LOW Level Input oltage (Note 2) Max OH HIGH Level Output oltage ; I OL = 100 A = 2.3 ; I OH = -8 ma 1.8 = 2.7 ; I OH = -12 ma 2.2 = 3.0 ; I OH = -18 ma 2.4 = 3.0 ; I OH = -24 ma 2.2 OL LOW Level Output oltage ; I OL = 100 A 0.2 = 2.3 ; I OL = 8 ma 0.6 = 2.7 ; I OL = 12 ma 0.4 = 3.0 ; I OL = 16 ma 0.4 = 3.0 ; I OL = 24 ma 0.55 I I Input Leakage Current ; 0 I 5.5 ±5.0 A I OZ 3-State Output Current ; 0 O 5.5 ; I = IH or IL ±5.0 A I OFF Power-Off Leakage Current = 0 ; I or O = A I CC uiescent Supply Current ; I = GN or 20 A ; 3.6 I or O 5.5 ±20 A I CC Increase in I CC per Input ; IH = A 2. These values of I are used to test C electrical characteristics only. Unit AC CHARACTERISTICS t R = t F = 2.5 ; C L = 50 pf; R L = 500 T A = -55 C to +125 C = 3.3 ± 0.3 C L = 50 pf = 2.7 C L = 50 pf = 2.5 ± 0.2 C L = 30 pf Symbol Parameter Waveform t PLH t PHL Propagation elay 1 n to O n Min Max Min Max Min Max Unit t PLH t PHL Propagation elay 3 LE to O n t PZH t PZL Output Enable Time to High and Low Level t PHZ t PLZ Output isable Time From High and Low Level t s Setup Time, HIGH or LOW n to LE t h Hold Time, HIGH or LOW n to LE t w LE Pulse Width, HIGH t OSHL t OSLH Output-to-Output Skew (Note 3) 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ); parameter guaranteed by design

5 YNAMIC SWITCHING CHARACTERISTICS Symbol Characteristic Condition OLP ynamic LOW Peak oltage (Note 4) = 3.3, C L = 50 pf, IH = 3.3, IL = 0 = 2.5, C L = 30 pf, IH = 2.5, IL = 0 T A = +25 C Min Typ Max Unit OL ynamic LOW alley oltage (Note 4) = 3.3, C L = 50 pf, IH = 3.3, IL = 0 = 2.5, C L = 30 pf, IH = 2.5, IL = 0 4. Number of outputs defined as n. Measured with n-1 outputs switching from HIGH-to-LOW or LOW-to-HIGH. The remaining output is measured in the LOW state. CAPACITIE CHARACTERISTICS Symbol Parameter Condition Typical Unit C IN Input Capacitance = 3.3, I = 0 or 7 pf C OUT Output Capacitance = 3.3, I = 0 or 8 pf C P Power issipation Capacitance 10 MHz, = 3.3, I = 0 or 20 pf n mi t PHL mi t PLH WAEFORM 1 - PROPAGATION ELAYS t R = t F = 2.5, 10% to 90%; f = 1 MHz; t W = OH OL OEn n mi t PZH t PHZ mi 0 OH HZ LEn t s t w t h 0 0 t PZL t PLZ t PLH, t PHL OH LZ OL OL WAEFORM 2 - OUTPUT ENABLE AN ISABLE TIMES t R = t F = 2.5, 10% to 90%; f = 1 MHz; t W = 500 WAEFORM 3 - LE to PROPAGATION ELAYS, LE MINIMUM PULSE WITH, n to LE SETUP AN HOL TIMES t R = t F = 2.5, 10% to 90%; f = 1 MHz; t W = 500 except when noted Figure 3. AC Waveforms Table 2. AC WAEFORMS Symbol 3.3 ± mi / 2 / 2 HZ OL OL OL LZ OH OH OH

6 PULSE GENERATOR UT R 1 6 or 2 OPEN GN R T C L R L Figure 4. Test Circuit Table 3. TEST CIRCUIT t PLH, t PHL t PZL, t PLZ TEST SWITCH Open 6 at = at = Open Collector/rain t PLH and t PHL t PZH, t PHZ 6 GN C L = 50 pf at = or equivalent (includes jig and probe capacitance) C L = 30 pf at = or equivalent (includes jig and probe capacitance) R L = R 1 = 500 or equivalent R T = Z OUT of pulse generator (typically 50 ) 6

7 PACKAGE IMENSIONS TSSOP- T SUFFIX CASE ISSUE A S U (0.010) M T L X K REF 0.12 (0.005) M T U S S B -U- J N J1 K K1 ÇÇÇ ÉÉÉ SECTION N-N NOTES: 1. IMENSIONING AN TOLERANCING PER ANSI Y14.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS A AN B O NOT INCLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.15 (0.006) PER SIE. 4. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. IMENSIONS A AN B ARE TO BE ETERMINE AT ATUM PLANE -W-. PIN 1 IENT. C A -- G H N ETAIL E F ETAIL E M 0.25 (0.010) (0.003) -T- SEATING PLANE -W- MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.50 BSC BSC H J J K K L M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74LCX16373/

MC74LCX Low-Voltage CMOS 16-Bit Transparent Latch. With 5 V Tolerant Inputs and Outputs (3 State, Non Inverting)

MC74LCX Low-Voltage CMOS 16-Bit Transparent Latch. With 5 V Tolerant Inputs and Outputs (3 State, Non Inverting) Low-oltage CMOS 6-Bit Traparent Latch With 5 Tolerant Inputs and Outputs (3 State, Non Inverting) The MC74LCX6373 is a high performance, non inverting 6 bit traparent latch operating from a 2.3 to 3.6