MC74HC157A. Quad 2-Input Data Selectors/Multiplexers. High Performance Silicon Gate CMOS

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1 Quad -Input Data Selectors/Multiplexers High Performance Silicon Gate CMOS The MCHCA is identical in pinout to the S. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with STT outputs. This device routes nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in noninverted form. A high level on the Output Enable input sets all four Y outputs to a low level. Features Output Drive Capability: 0 STT oads Outputs Directly Interface to CMOS, NMOS, and TT Operating oltage Range: to ow Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. A Chip Complexity: 8 FETs or 0. Equivalent Gates N Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant NIBBE A INPUTS NIBBE B INPUTS A0 A A A B0 B B B SEECT ENABE 0 9 Figure. ogic Diagram Y0 Y Y Y DATA S PIN = PIN 8 = SOIC D SUFFIX CASE B SEECT TSSOP DT SUFFIX CASE 98F MARKING DIAGRAMS HCAG AWYWW SOIC PIN ASSIGNMENT A0 B0 Y0 A B Y 8 0 HC A AYW A = Assembly ocation, W = Wafer ot Y, YY = Year W, WW = Work Week G or = Pb Free Package TSSOP (Note: Microdot may be in either location) 9 ENABE A B Y A B Y FUNCTION TABE Inputs Output Outputs Enable Select Y0 Y H X H A0 A B0 B X = don t care A0 A, B0 B = the levels of the respective Data Word Inputs. ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page of this data sheet. Semiconductor Components Industries, C, 0 August, 0 Rev. Publication Order Number: MCHCA/D

2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎ alue ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply oltage (Referenced to ) ÎÎÎÎÎ 0. to +.0 ÎÎÎ ÎÎÎÎ in ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input oltage (Referenced to ) ÎÎÎÎÎ 0. to + 0.ÎÎÎ ÎÎÎÎ out ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output oltage (Referenced to ) ÎÎÎÎÎ 0. to + 0.ÎÎÎ ÎÎÎÎ I in ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Current, per Pin ÎÎÎÎÎ ±0 ÎÎÎ ma ÎÎÎÎ I out ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Current, per Pin ÎÎÎÎÎ ± ÎÎÎ ma ÎÎÎÎ I CC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Current, and Pi ÎÎÎÎÎ ±0 ÎÎÎ ma ÎÎÎÎ P D ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, SOIC Package ÎÎÎÎÎ 00 ÎÎÎ mw TSSOP Package 0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ T ÎÎÎÎ stg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature to + 0 ÎÎÎÎÎÎÎ C T ÎÎÎÎ ead Temperature, mm from Case for 0 Seconds ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ C ÎÎÎÎÎ ÎÎÎ (SOIC or TSSOP Package) 0 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating: SOIC Package: mw/ C from to C TSSOP Package:. mw/ C from to C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply oltage (Referenced to ) in, out DC Input oltage, Output oltage (Referenced to ) 0 T A Operating Temperature, All Package Types + C t r, t f Input Rise and Fall Time = (Figure ) = = Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability

3 DC EECTRICA CHARACTERISTICS (oltages Referenced to ) Symbol Parameter Test Conditio IH I OH O Minimum High evel Input oltage Maximum ow evel Input oltage Minimum High evel Output oltage Maximum ow evel Output oltage out = I out 0 A out = I out 0 A in = IH I out 0 A in = IH in = I I out 0 A in = I I out. ma I out ma I out.8 ma I out. ma I out ma I out.8 ma Guaranteed imit to C 8 C C Unit I in Maximum Input eakage Current in = or ± ±.0 ±.0 A I OZ Maximum Three State eakage Current Output in High Impedance State in = I or IH out = or ±0. ±.0 ±0 A I CC Maximum Quiescent Supply Current (per Package) in = or I out = 0 A A AC EECTRICA CHARACTERISTICS (C = 0 pf, Input t r = t f = ) Guaranteed imit Symbol Parameter to C 8 C C Unit t PH, Maximum Propagation Delay, Input A or B to Output Y (Figures and ) t PH, Maximum Propagation Delay, Select to Output Y (Figures and ) t PH, Maximum Propagation Delay, Output Enable to Output Y (Figures and ) t TH, t TH Maximum Output Traition Time, Any Output (Figures and ) C in Maximum Input Capacitance pf C, =.0 C PD Power Dissipation Capacitance (Per Package)* * Used to determine the no load dynamic power coumption: P D = C PD f + I CC. pf

4 PIN DESCRIPTIONS INPUTS A0, A, A, A (Pi,,, ) Nibble A inputs. The data present on these pi is traferred to the outputs when the Select input is at a low level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form. B0, B, B, B (Pi,, 0, ) Nibble B inputs. The data present on these pi is traferred to the outputs when the Select input is at a high level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form. S Y0, Y, Y, Y (Pi,, 9, ) Data outputs. The selected input Nibble is presented at these outputs when the Output Enable input is at a low level. The data present on these pi is in its noninverted form. For the Output Enable input at a high level, the outputs are at a low level. CONTRO INPUTS Select (Pin ) Nibble select. This input determines the data word to be traferred to the outputs. A low level on this input selects the A inputs and a high level selects the B inputs. Output Enable (Pin ) Output Enable input. A low level on this input allows the selected input data to be presented at the outputs. A high level on this input sets all outputs to a low level. SWITCHING WAEFORMS t r t f INPUT A OR B 0% t PH Y 0% SEECT Y t PH t r t f 0% 0% t TH t TH t TH t TH Figure. HCA Figure. Y versus Selected, Noninverted ENABE 0% t r t f Y 0% t PH t TH t TH Figure. HCA TEST POINT DEICE UNDER TEST C * *Includes all probe and jig capacitance Figure. Test Circuit

5 EXPANDED OGIC DIAGRAM A0 B0 Y0 NIBBE S A B A B 0 9 Y Y DATA S A B ENABE SEECT Y ORDERING INFORMATION Device Package Shipping MCHCADG MCHCADRG MCHCADTRG NHCADRG* SOIC SOIC TSSOP SOIC 8 Units / Rail 00 / Tape & Reel 00 / Tape & Reel 00 / Tape & Reel NHCADTRG* TSSOP 00 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *N Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable

6 PACKAGE DIMENSIONS TSSOP CASE 98F ISSUE B (0.00) T (0.00) T 0 (0.00) T SEATING PANE U PIN IDENT. U D S S X / C X K REF 0 (0.00) M T U S S K 9 8 A G J K ÇÇÇ ÉÉÉ B SECTION N N U J N 0. (0.00) M N F DETAI E H DETAI E SODERING FOOTPRINT.0 W NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, 98.. CONTROING DIMENSION: MIIMETER.. DIMENSION A DOES NOT INCUDE MOD FASH. PROTRUSIONS OR GATE BURRS. MOD FASH OR GATE BURRS SHA NOT EXCEED (0.00) PER SIDE.. DIMENSION B DOES NOT INCUDE INTEREAD FASH OR PROTRUSION. INTEREAD FASH OR PROTRUSION SHA NOT EXCEED 0. (0.00) PER SIDE.. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SHA BE 0.08 (0.00) TOTA IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIA CONDITION.. TERMINA NUMBERS ARE SHOWN FOR REFERENCE ONY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0. BSC 0.0 BSC H J J K K BSC 0. BSC M PITCH X 0. X. DIMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D.

7 PACKAGE DIMENSIONS A 9 8 B SOIC CASE B 0 ISSUE K P 8 P 0. (0.00) M B S NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, 98.. CONTROING DIMENSION: MIIMETER.. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION.. MAXIMUM MOD PROTRUSION (0.00) PER SIDE.. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SHA BE (0.00) TOTA IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIA CONDITION. MIIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G. BSC 0.00 BSC J K M 0 0 P R T SEATING PANE G D P 0. (0.00) M T B S A S K C M R X J F SODERING FOOTPRINT* 8X.0 X. X 0.8. PITCH 8 9 DIMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, C (SCIC) or its subsidiaries in the United States and/or other countries. SCIC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCIC s product/patent coverage may be accessed at Marking.pdf. SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any licee under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 80 USA Phone: 0 or Toll Free USA/Canada Fax: 0 or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative MCHCA/D