MC74HC540A. Octal 3-State Inverting Buffer/Line Driver/Line Receiver. High Performance Silicon Gate CMOS

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1 Octal 3-State Inverting Buffer/ine Driver/ine Receiver igh Performance Silicon Gate CMOS The MC74C540A is identical in pinout to the S540. The device inputs are compatible with Standard CMOS outputs. External pull up resistors make them compatible with STT outputs. The C540A is an octal inverting buffer/line driver/line receiver designed to be used with 3 state memory address drivers, clock drivers, and other bus oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active low output enables. The C540A is similar in function to the C54A, which has noninverting outputs. Features Output Drive Capability: 5 STT oads Outputs Directly Interface to CMOS, NMOS, and TT Operating oltage Range: to ow Input Current: A igh Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7 A Requirements Chip Complexity: 24 FETs or 3 Equivalent Gates N Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable These Devices are Pb Free and are RoS Compliant Data Inputs Output Enables A A2 A3 A4 A5 A6 A7 A8 OE OE Figure. ogic Diagram 8 Y 7 Y2 6 Y3 5 Y4 4 Y5 3 Y6 2 Y7 Y8 PIN = CC PIN 0 = GND Inverting Outputs SOIC DW SUFFI CASE 75D MARKING DIAGRAMS 74C540A AWYYWWG SOIC PIN ASSIGNMENT DT SUFFI CASE 948E CC OE2 Y Y2 Y3 Y4 Y5 Y6 Y7 Y C 540A AYW A = Assembly ocation W, = Wafer ot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 5 of this data sheet OE A A2 A3 A4 A5 A6 A7 A8 GND ead (Top iew) FUNCTION TABE Inputs OE OE2 A Z = igh Impedance = Don t Care Output Y Z Z Semiconductor Components Industries, C, 4 August, 4 Rev. Publication Order Number: MC74C540A/D

2 MAIMUM RATINGS Symbol Parameter alue Unit CC DC Supply oltage 0.5 to +7.0 I DC Input oltage 0.5 to CC O DC Output oltage (Note ) 0.5 O CC I IK DC Input Diode Current ± ma I OK DC Output Diode Current ±35 ma I O DC Output Sink Current ±35 ma I CC DC Supply Current per Supply Pin ±75 ma I GND DC Ground Current per Ground Pin ±75 ma T STG Storage Temperature Range 65 to +50 C T ead Temperature, mm from Case for 0 Seconds 260 C T J Junction Temperature Under Bias +50 C JA Thermal Resistance SOIC TSSOP C/W P D Power Dissipation in Still Air at 85 C SOIC TSSOP mw MS Moisture Seitivity evel F R Flammability Rating Oxygen Index: 30% 35% U in ESD ESD Withstand oltage uman Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) > 00 > 0 > 000 I ATCUP atchup Performance Above CC and Below GND at 85 C (Note 5) ±300 ma Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. I O absolute maximum rating must be observed. 2. Tested to EIA/JESD22 A4 A. 3. Tested to EIA/JESD22 A5 A. 4. Tested to JESD22 C0 A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) in, out DC Input oltage, Output oltage (Referenced to GND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 3) CC = CC = CC = Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 6. Unused inputs may not be left open. All inputs must be tied to a high or low logic input voltage level

3 DC CARACTERISTICS (oltages Referenced to GND) Symbol Parameter Condition I Minimum igh evel Input oltage out = I out A I Maximum ow evel Input oltage out = CC I out A O O Minimum igh evel Output oltage Maximum ow evel Output oltage in = I I out A in = I in = I I out A in = I I out 3.6 ma I out ma I out 7.8 ma I out 3.6 ma I out ma I out 7.8 ma CC Guaranteed imit 55 to 25 C 85 C 25 C Unit I in Maximum Input eakage Current in = CC or GND ± ±.0 ±.0 A I OZ Maximum Three State eakage Current Output in igh Impedance State in = I or I out = CC or GND ±0.5 ±5.0 ±0.0 A I CC Maximum Quiescent Supply Current (per Package) in = CC or GND I out = 0 A A AC CARACTERISTICS (C = 50 pf, Input t r = t f = 6 ) Symbol t P, t P t PZ, t PZ t PZ, t PZ t T, t T Parameter Maximum Propagation Delay, Input A to Output Y (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output Y (Figures 3 and 5) Maximum Propagation Delay, Output Enable to Output Y (Figures 3 and 5) Maximum Output Traition Time, Any Output (Figures 2 and 4) CC Guaranteed imit 55 to 25 C 85 C 25 C Unit C in Maximum Input Capacitance pf C out Maximum 3 State Output Capacitance (Output in igh Impedance State) pf C, CC = 5.0, EE = 0 C PD Power Dissipation Capacitance (Per Buffer) (Note 7) 7. Used to determine the no load dynamic power coumption: P D = C PD 2 CC f + I CC CC. 35 pf 3

4 t r t f OE or OE2 CC INPUT A t P 90% 0% t T 90% 0% CC GND t P t T t PZ t PZ t PZ t PZ 0% 90% GND IG IMPEDANCE O O IG IMPEDANCE Figure 2. Switching Waveform Figure 3. Switching Waveform TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C * DEICE UNDER TEST OUTPUT k C * CONNECT TO CC WEN TESTING t PZ AND t PZ. CONNECT TO GND WEN TESTING t PZ and t PZ. *Includes all probe and jig capacitance Figure 4. Test Circuit *Includes all probe and jig capacitance Figure 5. Test Circuit To 7 Other Inverters One of Eight Inverters CC INPUT A OE OE2 Figure 6. ogic Detail 4

5 PIN DESCRIPTIONS INPUTS A, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) Data input pi. Data on these pi appear in inverted form on the corresponding Y outputs, when the outputs are enabled. CONTROS OE, OE2 (PINS, 9) Output enables (active low). When a low voltage is applied to both of these pi, the outputs are enabled and the device functio as an inverter. When a high voltage is applied to either input, the outputs assume the high impedance state. OUTPUTS Y, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 8, 7, 6, 5, 4, 3, 2, ) Device outputs. Depending upon the state of the output enable pi, these outputs are either inverting outputs or high impedance outputs. ORDERING INFORMATION Device Package Shipping MC74C540ADWG SOIC WIDE 38 Units / Rail MC74C540ADWR2G MC74C540ADTR2G SOIC WIDE 000 Tape & Reel 2500 Tape & Reel N74C540ADTR2G* 2500 Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *N Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable 5

6 PACKAGE DIMENSIONS DT SUFFI CASE 948E 02 ISSUE C 5 (0.006) T 5 (0.006) T U 2 /2 PIN IDENT U S S C 00 (0.004) T SEATING PANE K REF 0 (0.004) M T U S S 0 A D G B U N J J N K K ÍÍÍÍ ÍÍÍÍ SODERING FOOTPRINT* 7.06 SECTION N N 0.25 (0.00) M NOTES:. DIMENSIONING AND TOERANCING PER ANSI YM, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS, PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT ECEED 5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT ECEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN ECESS OF TE K DIMENSION AT MAIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. F MIIMETERS INCES DIM MIN MA MIN MA DETAI E A B C W D F G 0.65 BSC BSC J DETAI E J K K BSC BSC M PITC DIMENSIONS: MIIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 6

7 PACKAGE DIMENSIONS SOIC DW SUFFI CASE 75D 05 ISSUE G M B M D E A h 45 NOTES:. DIMENSIONS ARE IN MIIMETERS. 2. INTERPRET DIMENSIONS AND TOERANCES PER ASME YM, DIMENSIONS D AND E DO NOT INCUDE MOD PROTRUSION. 4. MAIMUM MOD PROTRUSION 5 PER SIDE. 5. DIMENSION B DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE PROTRUSION SA BE 3 TOTA IN ECESS OF B DIMENSION AT MAIMUM MATERIA CONDITION. B 0.25 M T A S 8 e 0 B B S A A T SEATING PANE C MIIMETERS DIM MIN MA A A B C D E e.27 BSC h ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, C (SCIC) or its subsidiaries in the United States and/or other countries. SCIC ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCIC s product/patent coverage may be accessed at Marking.pdf. SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any licee under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative MC74C540A/D