MC74VHC1G125. Noninverting 3 State Buffer
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1 MC74CG2 Noninverting 3 State Buffer The MC74CG2 is an advanced high speed CMOS noninverting 3 state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffered 3 state output which provides high noise immunity and stable output. The MC74CG2 input structure provides protection when voltages up to 7 are applied, regardless of the supply voltage. This allows the MC74CG2 to be used to interface circuits to 3 circuits. Features igh Speed: t PD = 3. ns (Typ) at CC = ow Power Dissipation: I CC = A (Max) at T A = 2 C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard ogic Families Chip Complexity: FETs = 8; Equivalent Gates = Pb Free Packages are Available SC 88A/SOT 33/SC 70 DF SUFFIX CASE 49A TSOP /SOT 23/SC 9 DT SUFFIX CASE 483 MARKING DIAGRAMS M W0 M W0 M IN A 2 CC W0 = Device Code M = Date Code* = Pb Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. GND 3 4 OUT Y PIN ASSIGNMENT Figure. Pinout (Top iew) 2 IN A 3 GND 4 OUT Y CC IN A EN OUT Y A Input FUNCTION TABE Input Y Output Figure 2. ogic Symbol X Z ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Semiconductor Components Industries, C, 2007 Publication Order Number: MC74CG2/D
2 MC74CG2 MAXIMUM RATINGS Symbol Characteristics alue Unit CC DC Supply oltage 0. to +7.0 IN DC Input oltage 0. to +7.0 OUT DC Output oltage CC = 0 igh or ow State 0. to to CC + 0. I IK Input Diode Current 20 ma I OK Output Diode Current OUT < GND; OUT > CC +20 ma I OUT DC Output Current, per Pin +2 ma I CC DC Supply Current, CC and GND +0 ma P D Power Dissipation in Still Air SC 88A, TSOP 200 mw JA Thermal Resistance SC 88A, TSOP 333 C/W T ead Temperature, mm from Case for 0 secs 260 C T J Junction Temperature Under Bias +0 C T stg Storage Temperature 6 to +0 C ESD ESD Withstand oltage uman Body Model (Note ) Machine Model (Note 2) Charged Device Model (Note 3) > 2000 > 200 N/A I atchup atchup Performance Above CC and Below GND at 2 C (Note 4) 00 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Tested to EIA/JESD22 A4 A. 2. Tested to EIA/JESD22 A A. 3. Tested to JESD22 C0 A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit CC DC Supply oltage. IN DC Input oltage 0.0. OUT DC Output oltage 0.0 CC T A Operating Temperature Range +2 C t r, t f Input Rise and Fall Time CC = CC = ns/ Device Junction Temperature versus Time to % Bond Failures Junction Temperature C Time, ours Time, Years 80,032, , , , , , ,900.0 NORMAIZED FAIURE RATE FAIURE RATE OF PASTIC = CERAMIC UNTI INTERMETAICS OCCUR TJ = 30 C TJ = 20 C TJ = 0 C TJ = 00 C TJ = 90 C TJ = 80 C TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature 2
3 MC74CG2 DC EECTRICA CARACTERISTICS Symbol Parameter Test Conditions I I O O I OZ I IN I CC Minimum igh evel Input oltage Maximum ow evel Input oltage Minimum igh evel Output oltage IN = I or I Maximum ow evel Output oltage IN = I or I Maximum 3 State eakage Current Maximum Input eakage Current Maximum Quiescent Supply Current IN = I or I I O = 0 A IN = I or I I O = 4 ma I O = 8 ma IN = I or I I O = 0 A IN = I or I I O = 4 ma I O = 8 ma IN = I or I OUT = CC or GND IN =. or GND CC () T A = 2 C T A 8 C T A 2 C Min Typ Max Min Max Min Max ±0.2 0 to Unit A ± ±.0.0 A IN = CC or GND A AC EECTRICA CARACTERISTICS C load = 0 pf, Input t r = t f = ns Î Î T ÎÎ A = 2 C T A 8 C T A 2 C ÎÎ Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit Î t P, Maximum Propagation CC = 3.3 ± 0.3 C = pf Î t P Î Delay, Input A to Y ÎÎ C = 0 pf Î ÎÎ 9. Î ÎÎ ns Î 6.0 ÎÎ (Figures 3 and 4) CC =.0 ± 0. C = pf ÎÎ 3.. Î ÎÎ C = 0 pf ÎÎ t Î PZ, Maximum Output t PZ Î Enable Time, ÎÎ CC = 3.3 ± 0.3 C = pf R = 000 C = 0 pf Î ÎÎ 9. Î ÎÎ. ns.0 ÎÎ Input to Y Î (Figures 4 and ) ÎÎ CC =.0 ± 0. C = pf ÎÎ 3.. Î ÎÎ R = 000 C = 0 pf t Î PZ, Maximum Output t PZ Î Disable Time, ÎÎ CC = 3.3 ± 0.3 C = pf R 000 C = 0 pf Î. 4. ns ÎÎ Î Input to Y ÎÎ ÎÎ (Figures 4 and ) CC =.0 ± 0. C = pf R = 000 C = 0 pf Î Î 0.0 Î ÎÎ C Î IN Î Maximum Input Î pf Capacitance Î C OUT Î Maximum 3 State Output Î Capacitance (Output in Î 6.0 pf igh Impedance State) 2 C, CC =.0 C PD Power Dissipation Capacitance (Note ) 8.0 pf. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC(OPR) = C PD CC f in + I CC. C PD is used to determine the no load dynamic power consumption; P D = C PD 2 CC f in + I CC CC. 3
4 MC74CG2 SWITCING WAEFORMS 0% CC GND A Y t P 0% CC 0% t P CC GND Y Y t PZ t PZ 0% CC t PZ t PZ 0% CC IG IMPEDANCE O O 0.3 IG IMPEDANCE Figure 4. Switching Wave Forms Figure. DEICE UNDER TEST OUTPUT TEST POINT C * DEICE UNDER TEST TEST POINT k OUTPUT C * CONNECT TO CC WEN TESTING t PZ AND t PZ. CONNECT TO GND WEN TESTING t PZ AND t PZ. *Includes all probe and jig capacitance Figure 6. Test Circuit *Includes all probe and jig capacitance Figure 7. Test Circuit INPUT Figure 8. Input Equivalent Circuit ORDERING INFORMATION MC74CG2DFT M74CG2DFTG Device Package Shipping SC 88A/SOT 33/SC 70 SC 88A/SOT 33/SC 70 (Pb Free) MC74CG2DFT2 M74CG2DFT2G SC 88A/SOT 33/SC 70 TSC 88A/SOT 33/SC 70 (Pb Free) 3000 Units / Tape & Reel MC74CG2DTT M74CG2DTTG TSOP /SOT 23/SC 9 TSOP /SOT 23/SC 9 (Pb Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 4
5 MC74CG2 PACKAGE DIMENSIONS SC 88A, SOT 33, SC 70 CASE 49A 02 ISSUE J S A G 4 B 2 3 D P 0.2 (0.008) M B M N NOTES:. DIMENSIONING AND TRANCING PER ANSI Y4.M, CONTROING DIMENSION: INC A 0 OBSTE. NEW STANDARD 49A DIMENSIONS A AND B DO NOT INCUDE MOD FAS, PROTRUSIONS, OR GATE BURRS. INCES MIIMETERS DIM MIN MAX MIN MAX A B C D G BSC 0.6 BSC J K N REF 0.20 REF S C J K SODERING FOOTPRINT* SCAE 20: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D.
6 MC74CG2 PACKAGE DIMENSIONS TSOP CASE ISSUE F 2X 2X NOTE 0 T 0.20 T G A B C D X 0.20 C A B T S SEATING PANE J K DETAI Z M DETAI Z NOTES:. DIMENSIONING AND TRANCING PER ASME Y4.M, CONTROING DIMENSION: MIIMETERS. 3. MAXIMUM EAD TICKNESS INCUDES EAD FINIS TICKNESS. MINIMUM EAD TICKNESS IS TE MINIMUM TICKNESS OF BASE MATERIA. 4. DIMENSIONS A AND B DO NOT INCUDE MOD FAS, PROTRUSIONS, OR GATE BURRS.. OPTIONA CONSTRUCTION: AN ADDITIONA TRIMMED EAD IS AOWED IN TIS OCATION. TRIMMED EAD NOT TO EXTEND MORE TAN 0.2 FROM BODY. MIIMETERS DIM MIN MAX A 0 BSC B.0 BSC C D G 0.9 BSC J K M 0 0 S 0 SODERING FOOTPRINT* SCAE 0: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. 6 MC74CG2/D
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MC74VHC1GT00. Single 2-Input NAND Gate/ CMOS Logic Level Shifter. LSTTL Compatible Inputs
M74GT00 Single 2-Input NND Gate/ MOS ogic evel Shifter STT ompatible Inputs The M74GT00 is a single gate 2 input NND fabricated with silicon gate MOS technology. The internal circuit is composed of multiple
FST Bit Bus Switch
FST32 4-Bit Bus Switch The ON Semiconductor FST32 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and. Volts. The device exhibits extremely low R ON and adds
NL17SZ17. Single Non-Inverting Buffer with Schmitt Trigger
NL7SZ7 Single Non-Inverting Buffer with Schmitt Trigger The NL7SZ7 is a single Non inverting Schmitt Trigger Buffer in two tiny footprint packages. The device performs much as LCX multi gate products in
MC74AC132, MC74ACT132. Quad 2 Input NAND Schmitt Trigger
MC32, MC32 Quad 2 Input NAND Schmitt Trigger The MC/32 contains four 2 input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter free output signals.
MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
UNISONIC TECHNOLOGIES CO., LTD
U74ACT157 UNISONIC TECNOOGIES CO., TD QUADRUPE 2-INE TO 1-INE DATA SEECTOR/ MUTIPEER DESCRIPTION The U74ACT157 is a quadruple 2-line to 1-line data selector/multiplexer. When G is high, all outputs are
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
MC74VHC1G125, MC74VHC1GT125. Noninverting 3-State Buffer
MC7HCG2, MC7HCGT2 Noninverting 3-State Buffer The MC7HCG2 / MC7HCGT2 is a single noninverting 3state buffer in tiny footprint packages. The MC7HCG2 has CMOSlevel input thresholds while the MC7HCGT2 has
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS
MC74HC139A. Dual 1 of 4 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
MC74HC39A Dual of 4 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC39A is identical in pinout to the LS39. The device inputs are compatible with standard CMOS outputs; with pull up
MC74HCT573A/D. Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter
MC74VHCT245A. Octal Bus Transceiver
Octal Bus Transceiver The MC4HCT245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky
MC74LV594A. 8-Bit Shift Register with Output Register
8-Bit Shift Register with Output Register The MC74LV594A is an 8 bit shift register designed for 2 V to 6.0 V V CC operation. The device contain an 8 bit serial in, parallel out shift register that feeds
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
MC74VHCT541A. Octal Bus Buffer
Octal Bus Buffer The is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining
MC74VHCT244A. Octal Bus Buffer/Line Driver with 3-State Outputs
Octal Bus Buffer/ine Driver with 3-State Outputs The M74VHT244A is an advanced high speed MOS octal bus buffer fabricated with silicon gate MOS technology. It achieves high speed operation similar to equivalent
MC74LCX74. Low-Voltage CMOS Dual D-Type Flip-Flop. With 5 V Tolerant Inputs
Low-oltage CMOS Dual D-Type Flip-Flop With 5 Tolerant Inputs The MC74LCX74 is a high performance, dual D type flip flop with asynchronous clear and set inputs and complementary (O, O) outputs. It operates
MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Pin Assignment VHCT139A AWLYYWW SOIC 16 D SUFFIX CASE 751B VHCT139A AWLYWW
The MC74HCT139A is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices
NL17SG07. Buffer with Open Drain. Output Y
NL7SG07 Buffer with Open Drain Output The NL7SG07 MiniGate is an advanced high speed CMOS Buffer with Open Drain Output in ultra small footprint. The NL7SG07 input structures provides protection when voltages
SGM7SZ00 Small Logic Two-Input NAND Gate
GENERAL DESCRIPTION The SGM7SZ00 is a single two-input NAND gate from SGMICRO s Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive
Obsolete Product(s) - Obsolete Product(s)
8-INPUT NAND GATE HIGH SPEED: t PD = 13ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: I
M74HC20TTR DUAL 4-INPUT NAND GATE
DUAL 4-INPUT NAND GATE HIGH SPEED: t PD = 9ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
MC74HC244A. Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver. High Performance Silicon Gate CMOS
Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;