INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines File under Integrated Circuits, IC06 December 1990

2 FEATURES Non-inverting outputs Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The are hex non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (ny) are controlled by the output enable inputs (OE 1, OE 2 ). A IG on OE n causes the outputs to assume a high impedance OFF-state. The 365 is identical to the 366 but has non-inverting outputs. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay C = 15 pf; V CC =5 V 9 11 ns na to ny C I input capacitance 3,5 3,5 pf C PD power dissipation capacitance per buffer notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December

3 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1, 15 OE 1, OE 2 output enable inputs (active OW) 2, 4, 6, 10, 12, 14 1A to 6A data inputs 3, 5, 7, 9, 11, 13 1Y to 6Y data outputs 8 GND ground (0 V) 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Fig.3 IEC logic symbol. December

4 FUNCTION TABE INPUTS Notes 1. = IG voltage level = OW voltage level = don t care Z = high impedance OFF-state OUTPUT OE 1 OE 2 na ny Z Z Fig.4 Functional diagram. Fig.5 ogic diagram. December

5 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t PZ / t PZ t PZ / t PZ PARAMETER propagation delay na to ny 3-state output enable time 3-state output disable time T amb ( C) 74C to to+125 min. typ. max. min. max. min. max t T / t T output transition time UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.6 Fig.7 Fig.7 Fig.6 December

6 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE 1 OE 2 na UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t PZ / t PZ t PZ / t PZ PARAMETER propagation delay na to ny 3-state output enable time 3-state output disable time T amb ( C) 74CT to to+125 min. typ. max. min. max. min. max. UNIT TEST CONDITIONS V CC (V) ns Fig ns Fig ns Fig.7 t T / t T output transition time ns Fig.6 WAVEFORMS December

7 AC WAVEFORMS (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the input (na) to output (ny) propagation delays and the output transition times. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

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