INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines 74C/CT454 4-to-6 line decoder/demultiplexer with File under Integrated Circuits, IC06 September 993

2 4-to-6 line decoder/demultiplexer with 74C/CT454 FEATURES Non-inverting outputs Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT454 are high-speed Si-gate CMOS devices and are pin compatible with 454 of the 4000B series. They are specified in compliance with JEDEC standard no. 7A. The 74C/CT454 are 4-to-6 line decoders/demultiplexers having four binary weighted address inputs (A 0 to A 3 ), with latches, a latch enable input (E), and an active OW enable input (E). The 6 outputs (Q 0 to Q 5 ) are mutually exclusive active IG. When E is IG, the selected output is determined by the data on A n. When E goes OW, the last data present at A n are stored in the latches and the outputs remain stable. When E is OW, the selected output, determined by the contents of the latch, is IG. At E IG, all outputs are OW. The enable input (E) does not affect the state of the latch. When the 454 is used as a demultiplexer, E is the data input and A 0 to A 3 are the address inputs. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P A n to Q n C = 5 pf; V CC =5 V ns C I input capacitance pf C PD power dissipation capacitance per package notes and pf Notes. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. September 993 2

3 4-to-6 line decoder/demultiplexer with 74C/CT454 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION E latch enable input (active IG) 2, 3, 2, 22 A 0 to A 3 address inputs, 9, 0, 8, 7, 6, 5, 4, 8, 7, 20, 9, 4, 3, 6, 5 Q 0 to Q 5 multiplexer outputs (active IG) 2 GND ground (0 V) 23 E enable input (active OW) 24 V CC positive supply voltage Fig. Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. September 993 3

4 September Philips Semiconductors 4-to-6 line decoder/demultiplexer with 74C/CT454 Fig.4 Functional diagram. APPICATIONS Digital multiplexing Address decoding exadecimal/bcd decoding FUNCTION TABE Notes. E = IG = IG voltage level = OW voltage level X = don t care INPUTS OUTPUTS E A 0 A A 2 A 3 Q 0 Q Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 Q 0 Q Q 2 Q 3 Q 4 Q 5 X X X X

5 4-to-6 line decoder/demultiplexer with 74C/CT454 Fig.5 ogic diagram. September 993 5

6 4-to-6 line decoder/demultiplexer with 74C/CT454 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t P / t P t P / t P PARAMETER 74 A n to Q n E to Q n E to Q n 5 2 t T / t T output transition time t W t su t h latch enable pulse width IG set-up time A n to E hold time A n to E T amb ( C) 74C to to +25 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.6 Fig.6 Fig.6 Fig.6 Fig.7 Fig.7 Fig.7 September 993 6

7 4-to-6 line decoder/demultiplexer with 74C/CT454 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT A n E E UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t P / t P t P / t P t T / t T T amb ( C) TEST CONDITIONS 74CT PARAMETER UNIT V WAVEFORMS to to +25 CC (V) min. typ. max. min. max. min. max. A n to Q n ns Fig.6 E to Q n ns Fig.6 E to Q n ns Fig.6 output transition time ns Fig.6 t W t su t h latch enable pulse width IG set-up time A n to E hold time A n to E ns Fig ns Fig ns Fig.7 September 993 7

8 4-to-6 line decoder/demultiplexer with 74C/CT454 AC WAVEFORMS () C : V M = 50%; V I = GND to V CC. CT: V M =.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the input (A n, E, E) to output (Q n ) s and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. () C : V M = 50%; V I = GND to V CC. CT: V M =.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the minimum pulse width of the latch enable input (E) and the set-up and hold times for E to A n. Set-up and hold times are shown as positive values but may be specified as negative values. September 993 8

9 4-to-6 line decoder/demultiplexer with 74C/CT454 APPICATION INFORMATION Fig.8 Code-to-code conversion; hexadecimal to BCD. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. September 993 9

10 74C/CT454 Packaging Information Type Number Orderable Part Number Package Name 74C454DB 74C454DB,8 SSOP24 74C454DB 74C454DB,2 SSOP24 74C454D 74C454D,653 SO24 74C454D 74C454D,652 SO24 74C454PW 74C454PW,8 TSSOP24 74C454PW 74C454PW,2 TSSOP24 74C454N 74C454N,652 DIP24 74CT454DB 74CT454DB,8 SSOP24 74CT454DB 74CT454DB,2 SSOP24 74CT454D 74CT454D,653 SO24 74CT454D 74CT454D,652 SO24 74CT454PW 74CT454PW,8 TSSOP24 74CT454PW 74CT454PW,2 TSSOP24 74CT454N 74CT454N,652 DIP24

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic