INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines 74C/CT154 File under Integrated Circuits, IC06 September 1993

2 74C/CT154 FEATURES 16-line demultiplexing capability Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs 2-input enable gate for strobing or expansion Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT154 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT154 decoders accept four active IG binary address inputs and provide 16 mutually exclusive active OW outputs. The 2-input enable gate can be used to strobe the decoder to eliminate the normal decoding glitches on the outputs, or it can be used for the expansion of the decoder. The enable gate has two AND ed inputs which must be OW to enable the outputs. The 154 can be used as a 1-to-16 demultiplexer by using one of the enable inputs as the multiplexed data input. When the other enable is OW, the addressed output will follow the state of the applied data. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P/ t P propagation delay A n, E n to Y n C = 15 pf; V CC =5 V ns C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. September

3 74C/CT154 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17 Y 0 to Y 15 outputs (active OW) 18, 19 E 0, E 1 enable inputs (active OW) 12 GND ground (0 V) 23, 22, 21, 20 A 0 to A 3 address inputs 24 V CC positive supply voltage (a) (b) Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. September

4 September Philips Semiconductors 74C/CT154 FUNCTION TABE Note 1. = IG voltage level = OW voltage level = don t care INPUTS OUTPUTS E 0 E 1 A 0 A 1 A 2 A 3 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 8 Y 9 Y 10 Y 11 Y 12 Y 13 Y 14 Y 15 Fig.5 ogic diagram.

5 74C/CT154 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t P / t P PARAMETER propagation delay 36 A n to Y n propagation delay E n to Y n t T / t T output transition time T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) ns ns ns WAVEFORMS Fig.6 Fig.7 Figs 6 and 7 September

6 74C/CT154 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT OAD COEFFICIENT A n 1.0 E n 1.0 AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C = 50 pf T amb ( C) TEST CONDITIONS ns 4.5 Fig ns 4.5 Fig.7 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay A n to Y n t P / t P propagation delay E n to Y n t T / t T output transition time ns 4.5 Figs 6 and 7 September

7 74C/CT154 AC WAVEFORMS (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. (1) C : V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the address input (A n ) to output (Y n ) propagation delays and the output transition times. Fig.7 Waveforms showing the enable input (En) to output (Y n ) propagation delays and the output transition times. APPICATION INFORMATION Fig.8 1-of-16 decoder; OW level output is selected. Fig.9 1-of-16 demultiplexer; logic level on selected outputs follow the logic level on the data input. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. September

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS