INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS Logic Family Specificatio The IC6 74HC/HCT/HCU/HCMOS Logic Package Information The IC6 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT16 Presettable synchronous BCD decade counter; asynchronous reset File under Integrated Circuits, IC6 December 199

2 74HC/HCT16 FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive-edge triggered clock Asynchronous reset Output capability: standard I CC category: MSI GENERAL DESCRIPTION The 74HC/HCT16 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT16 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q to Q 3 ) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D to D 3 ) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q to Q 3 ) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC and CEP to CP, according to the following formula: f max = t P ( max) ( CP to TC) +t SU (CEP to CP) QUICK REFERENCE DATA GND = V; T amb =25 C; t r =t f = 6 SYMBOL PARAMETER CONDITIONS t PHL t PLH f max CP to Q n CP to TC MR to Q n MR to TC CET to TC CP to Q n CP to TC CET to TC maximum clock frequency HC C L =15pF; V CC =5V TYPICAL HCT UNIT MHz C I input capacitance pf C PD power dissipation notes 1 and 2 capacitance per package pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V CC 2 f i + (C L V CC 2 f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC 1.5 V December 199 2

3 74HC/HCT16 ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 MR asynchronous master reset (active LOW) 2 CP clock input (LOW-to-HIGH, edge-triggered) 3, 4, 5, 6 D to D 3 data inputs 7 CEP count enable input 8 GND ground ( V) 9 PE parallel enable input (active LOW) 1 CET count enable carry input, 13, 12, 11 Q to Q 3 flip-flop outputs 15 TC terminal count output 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 199 3

4 74HC/HCT16 Fig.4 Functional diagram. FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS MR CP CEP CET PE D n Q n TC reset (clear) L X X X X X L L parallel load H H X X X X I I I h L H L (1) count H h h h X count (1) hold H X I X h X q n (1) (do nothing) H X X I h X q n L Notes 1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH). H = HIGH voltage level h = HIGH voltage level one prior to the LOW-to-HIGH CP traition L = LOW voltage level I = LOW voltage level one prior to the LOW-to-HIGH CP traition q = lower case letters indicate the state of the referenced output one prior to the LOW-to-HIGH CP traition X = don t care = LOW-to-HIGH CP traition December 199 4

5 74HC/HCT16 Fig.5 State diagram. Fig.6 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two and three; inhibit. Fig.7 Logic diagram. December 199 5

6 74HC/HCT16 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specificatio. Output capability: standard I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = V; t r =t f = 6 ; C L = 5 pf SYMBOL t PHL / t PLH t PHL / t PLH t PHL t PHL t PHL / t PLH PARAMETER 61 CP to Q n CP to TC T amb ( C) 74HC to to +125 min. typ. max. min. max. min. max MR to Q n 25 2 MR to TC CET to TC t THL / t TLH output traition time t W t W t rem clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP D n to CP PE to CP UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig. 8 Fig. 8 Fig. 9 Fig. 9 Fig. 1 Figs 8 and 1 Fig. 8 Fig. 9 Fig. 9 Fig. 11 Fig. 11 December 199 6

7 74HC/HCT16 T amb ( C) TEST CONDITIONS SYMBOL PARAMETER 74HC to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS f max CEP, CET to CP D n to CP PE to CP CEP, CET to CP maximum clock pulse frequency MHz Fig. 12 Figs 11 and 12 Figs 11 and 12 Figs 11 and 12 Fig. 8 December 199 7

8 74HC/HCT16 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specificatio. Output capability: standard I CC category: MSI Note to HCT types The value of additional quiescenpply current ( I CC ) for unit load of 1 is given in the family specificatio. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT MR.95 CP.8 CEP.25 D n.25 CET 1.5 PT.3 December 199 8

9 74HC/HCT16 AC CHARACTERISTICS FOR 74HCT GND = V; t r =t f = 6 ; C L = 5 pf T amb ( C) TEST CONDITIONS Fig. 8 74HCT SYMBOL PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t PHL / t PLH CP to Q n t PHL Fig. 8 CP to TC t PLH Fig. 8 CP to TC t PHL Fig. 9 MR to Q n t PHL Fig. 9 MR to TC t PHL Fig. 1 CET to TC t PLH Fig. 1 CET to TC t THL / t TLH output traition time Figs 8 and 1 t W t W t rem f max clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP D n to CP PE to CP CEP, CET to CP D n to CP PE to CP CEP, CET to CP maximum clock pulse frequency Fig Fig Fig Fig Fig Fig Figs 11 and Figs 11 and 12 Figs 11 and MHz Fig. 8 PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines. December 199 9

10 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: 74HC16D,652 74HC16DB,112 74HC16DB,118 74HC16D,653 74HC16N,652 74HC16PW,112 74HC16PW,118 74HCT16D,652 74HCT16D,653 74HCT16N,652 74HCT16PW,112 74HCT16PW,118

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Important notice Dear Customer, On 7 February 7 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and