DATA SHEET. HEF40163B MSI 4-bit synchronous binary counter with synchronous reset. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC 4-bit synchronous binary counter with File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P 0 to P 3 ), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and (SR)), buffered outputs from all four bit positions (O 0 to O 3 ) and a terminal count output (TC). Operation is fully synchronous and occurs on the LOW to HIGH transition of CP. When PE is LOW, the next LOW to HIGH transition of CP loads data into the counter from P 0 to P 3. When PE is HIGH, the next LOW to HIGH transition of CP advances the counter to its next state only if both CEP and CET are HIGH; otherwise no change occurs in the state of the counter. TC is HIGH when the state of the counter is 15 (O 0 to O 3 = HIGH) and when CET is HIGH. A LOW on SR sets all outputs (O 0 to O 3 and TC) LOW on the next LOW to HIGH transition of CP, independent of the state of all other synchronous mode control inputs (CEP, CET and PE). Multistage synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages. CEP, CET, PE and SR must be stable only during the set-up time before the LOW to HIGH transition of CP. Fig.1 Functional diagram. FAMILY DATA, I DD LIMITS category See Family Specifications January

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4 PINNING PE P 0 to P 3 CEP CET CP SR O 0 to O 3 TC parallel enable input parallel data inputs count enable parallel input count enable trickle input clock input (LOW to HIGH, edge-triggered) input (active LOW) parallel outputs terminal count output Fig.3 Pinning diagram. P(N): 16-lead DIL; plastic (SOT38-1) D(F): 16-lead DIL; ceramic (cerdip) (SOT74) T(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America SYNCHRONOUS MODE SELECTION SR PE CEP CET MODE H L X X preset H H L X no change H H X L no change H H H H count L X X X reset Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial TERMINAL COUNT GENERATION CET (O 0 O 1 O 2 O 3 ) TC L L L L H L H L L H H H Note 1. TC = CET O 0 O 1 O 2 O 3 Fig.4 State diagram. January

5 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; input transition times 20 ns V DD V TYPICAL FORMULA FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays CP O n ns 83 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 34 ns + (0,23 ns/pf) C L ns 22 ns + (0,16 ns/pf) C L ns 88 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 34 ns + (0,23 ns/pf) C L ns 27 ns + (0,16 ns/pf) C L CP TC ns 103 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 44 ns + (0,23 ns/pf) C L ns 27 ns + (0,16 ns/pf) C L ns 113 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 44 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L CET TC ns 78 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 39 ns + (0,23 ns/pf) C L ns 27 ns + (0,16 ns/pf) C L ns 63 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 24 ns + (0,23 ns/pf) C L ns 17 ns + (0,16 ns/pf) C L Output transition times ns 10 ns + (1,0 ns/pf) C L HIGH to LOW 10 t THL ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L ns 10 ns + (1,0 ns/pf) C L LOW to HIGH 10 t TLH ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L January

6 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD SYMBOL MIN. TYP. MAX. V Minimum clock ns pulse width; LOW 10 t WCPL ns ns Set-up times ns P n CP 10 t su ns ns ns PE CP 10 t su ns ns ns CEP, CET CP 10 t su ns ns ns SR CP 10 t su ns ns Hold times ns P n CP 10 t hold ns ns ns PE CP 10 t hold 5 15 ns ns ns CEP, CET CP 10 t hold ns ns ns SR CP 10 t hold 5 5 ns ns Maximum clock 5 2,5 5 MHz pulse frequency 10 f max 7 14 MHz MHz see also waveforms Figs 5, 6, 7 and 8 January

7 Conditions PE = LOW P 0 to P 3 = HIGH Fig.5 Waveforms showing set-up and hold times for SR input and minimum CP pulse width. Condition: PE = SR = HIGH. Fig.6 Waveforms showing set-up times and hold times for CEP and CET inputs. January

8 Conditions PE = LOW SR = HIGH Fig.7 Waveforms showing set-up times and hold times for P n inputs. Condition SR = HIGH Fig.8 Waveforms showing set-up times and hold times for PE input. Note Set-up and hold times are shown as positive values but may be specified as negative values. January

9 Fig.9 Timing diagram. APPLICATION INFORMATION An example of an application for the is: Programmable binary counter. January

10 NOTE On the TC outputs, glitches can occur during counting. In totally synchronous mode they will not have any adverse affect. However the TC output in asynchronous mode can cause problems. Fig.10 Synchronous multi-stage counting scheme. January

DATA SHEET. HEF4520B MSI Dual binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4520B MSI Dual binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,