DATA SHEET. HEF4027B flip-flops Dual JK flip-flop. For a complete data sheet, please also download: INTEGRATED CIRCUITS

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Preston Welch
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1 INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is a dual JK flip-flop which is edge-triggered and features independent set direct (S D ), clear direct (C D ), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (C D ) and set-direct (S D ) are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FUNCTION TBLES INPUTS OUTPUTS S D C D CP J K O O H L X X X H L L H X X X L H H H X X X H H INPUTS OUTPUTS S D C D CP J K O n + 1 O n + 1 L L L L no change L L H L H L L L L H L H L L H H O n O n Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition O n + 1 = state after clock positive transition PINNING J,K CP S D C D O O synchronous inputs clock input (L to H edge-triggered) asynchronous set-direct input (active HIGH) asynchronous clear-direct input (active HIGH) true output complement output Fig.1 Functional diagram. P(N): 16-lead DIL; plastic (SOT38-1) D(F): 16-lead DIL; ceramic (cerdip) (SOT74) T(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North merica FMILY DT, I DD LIMITS category FLIP-FLOPS See Family Specifications Fig.2 Pinning diagram. January

3 Fig.3 Logic diagram (one flip-flop). C CHRCTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MX. TYPICL EXTRPOLTION FORMUL Propagation delays CP O, O ns 78 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 29 ns + (0,23 ns/pf) C L ns 22 ns + (0,16 ns/pf) C L ns 58 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 27 ns + (0,23 ns/pf) C L ns 22 ns + (0,16 ns/pf) C L S D O ns 43 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 19 ns + (0,23 ns/pf) C L ns 17 ns + (0,16 ns/pf) C L C D O ns 93 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 33 ns + (0,23 ns/pf) C L ns 27 ns + (0,16 ns/pf) C L S D O ns 113 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 44 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L January

4 V DD V SYMBOL MIN. TYP. MX. TYPICL EXTRPOLTION FORMUL C D O ns 48 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 24 ns + (0,23 ns/pf) C L ns 17 ns + (0,16 ns/pf) C L Output transition times ns 10 ns + (1,0 ns/pf) C L HIGH to LOW 10 t THL ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L ns 10 ns + (1,0 ns/pf) C L LOW to HIGH 10 t TLH ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L Set-up time ns J,K CP 10 t su ns ns Hold time ns J,K CP 10 t hold 20 0 ns ns Minimum clock ns pulse width; LOW 10 t WCPL ns ns Minimum S D,C D ns t pulse width; HIGH 10 WSDH, ns t WCDH ns Recovery time ns t for S RSD, D,C D ns t RCD ns Maximum clock MHz pulse frequency 10 f max MHz J = K = HIGH MHz see also waveforms Figs 4 and 5 see also waveforms Fig.4 V DD V TYPICL FORMUL FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) January

5 Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values. Fig.5 Waveforms showing recovery times for S D and C D ; minimum S D and C D pulse widths. PPLICTION INFORMTION Some examples of applications for the are: Registers Counters Control circuits January

6 Package information Package outlines SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E X c y H E v M Z 16 9 Q 2 1 ( ) 3 pin 1 index θ L p 1 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT E07S MS-012C January

7 Package information Package outlines DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 D M E seating plane 2 L 1 Z 16 e b b 1 9 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H Note 1. Plastic or metal protrusions of mm maximum per side are not included w (1) Z max OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT G09 MO-001E January

DATA SHEET. HEF4514B MSI 1-of-16 decoder/demultiplexer with input latches. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4514B MSI 1-of-16 decoder/demultiplexer with input latches. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,