DATA SHEET. HEF4022B MSI 4-stage divide-by-8 Johnson counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC 4-stage divide-by-8 Johnson counter File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is a with eight spike-free decoded active HIGH outputs (O 0 to O 7 ), an active LOW output from the most significant flip-flop (O 4-7 ), active HIGH and active LOW clock inputs (CP 0, CP 1 ) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW to HIGH transition at CP 0 while CP 1 is LOW or a HIGH to LOW transition at CP 1 while CP 0 is HIGH (see also function table). Either CP 0 or CP 1 may be used as clock input to the counter and the other clock input may be used as a clock enable input. When cascading counters, the O 4-7 output, which is LOW while the counter is in states, 4, 5, 6 and 7, can be used to drive the CP 0 input of the next counter. A HIGH on MR resets the counter to zero (O 0 = O 4-7 = HIGH; O 1 to O 7 = LOW) independent of the clock inputs (CP 0, CP 1 ). Automatic code correction of the counter is provided by an internal circuit, following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Fig.1 Functional diagram. P(N): 16-lead DIL; plastic (SOT38-1) D(F): 16-lead DIL; ceramic (cerdip) (SOT74) T(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, I DD LIMITS category See Family Specifications PINNING CP O CP 1 MR O 0 to O 7 O 4-7 clock input (LOW to HIGH; edge-triggered) clock input (HIGH to LOW; edge-triggered) master reset input decoded outputs carry output (active LOW) January

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4 FUNCTION TABLE MR CP 0 CP 1 OPERATION H X X O 0 = O 4-7 = H; O 1 to O 7 =L L H Counter advances L L Counter advances Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition L L X No change L X H No change L H No change L L No change AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays CP 0, CP 1 O n ns 168 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 64 ns + (0,23 ns/pf) C L ns 42 ns + (0,16 ns/pf) C L ns 218 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 84 ns + (0,23 ns/pf) C L ns 52 ns + (0,16 ns/pf) C L CP 0, CP 1 O ns 218 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 79 ns + (0,23 ns/pf) C L ns 52 ns + (0,16 ns/pf) C L ns 163 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 64 ns + (0,23 ns/pf) C L ns 42 ns + (0,16 ns/pf) C L MR O 1 to O ns 103 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 44 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L MR O ns 103 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 44 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L MR O ns 83 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 34 ns + (0,23 ns/pf) C L ns 27 ns + (0,16 ns/pf) C L Output transition times ns 10 ns + (1,0 ns/pf) C L HIGH to LOW 10 t THL ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L ns 10 ns + (1,0 ns/pf) C L LOW to HIGH 10 t TLH ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L January

5 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD SYMBOL MIN. TYP. MAX. V Hold times ns CP 0 CP 1 10 t hold ns ns ns CP 1 CP 0 10 t hold ns ns Minimum clock ns pulse width 10 t WCP ns ns Minimum MR ns pulse width; HIGH 10 t WMRH ns ns Recovery time ns for MR 10 t RMR 15 5 ns ns Maximum clock MHz pulse frequency 10 f max 8 16 MHz MHz see also waveforms Figs 4 and 5 V DD V TYPICAL FORMULA FOR P (µw) Dynamic power f i + (f o CL) V 2 DD where dissipation per f i + (f o CL) V 2 DD f i = input freq. (MHz) package (P) f i + (f o CL) V 2 DD f o = output freq. (MHz) C L = total load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) January

6 Fig.4 Waveforms showing hold times for CP 0 to CP 1 and CP 1 to CP 0. Hold times are shown as positive values, but may be specified as negative values. Conditions: CP 1 = LOW while CP 0 is triggered on a LOW to HIGH transition. t WCP and t RMR also apply when CP 0 = HIGH and CP 1 is triggered on a HIGH to LOW transition. Fig.5 Waveforms showing recovery time for MR; minimum CP 0 and MR pulse widths. January

7 Fig.6 Timing diagram. January

8 APPLICATION INFORMATION Some of the features of the are: High speed Spike-free decoded outputs Carry output for cascading Figure 7 shows a technique for extending the number of decoded output states for the. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). Fig.7 Counter expansion. January

DATA SHEET. HEF4520B MSI Dual binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4520B MSI Dual binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,