DATA SHEET. HEF4894B 12-stage shift-and-store register LED driver. For a complete data sheet, please also download: INTEGRATED CIRCUITS

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Download "DATA SHEET. HEF4894B 12-stage shift-and-store register LED driver. For a complete data sheet, please also download: INTEGRATED CIRCUITS"

Letitia Briggs
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1 INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC 12-stage shift-and-store register LED driver File under Integrated Circuits, IC04 January 1995

2 PPLICTIONS utomotive Industrial GENERL DESCRIPTION The is a 12 stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel LED driver outputs O 0 to O 11. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (EO) signal is HIGH. Two serial outputs (O s and O s ) are available for cascading a number of devices. Data is available at O s on positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at O s on the next negative-going clock edge and provides cascading devices when the clock rise time is slow. ORDERING ND PCKGE INFORMTION TYPE PCKGES NUMBER PINS PIN POSITION MTERIL CODE T 20 SO plastic SO20/SOT163 P 20 DIL plastic DIL20/SOT146 PINNING PIN SYMBOL NME ND FUNCTION 1 STR strobe input 2 D data input 3 CP clock input 4, 5, 6, 7, 8, 9, 18, O 0 to O 11 parallel outputs (open drain) 17, 16, 15, 14, V ss ground 11, 12 O s,o s serial outputs 19 EO output enable input 20 positive supply voltage FMILY DT See Family Specifications except for: Rating for DC current into any open-drain output: 40 m. I DD LIMITS category MSI: see Family Specifications. Preliminary pin assignment. Fig.1 Pinning diagram. Fig.2 Functional diagram. January

3 Fig.3 Logic diagram. FUNCTION TBLE INPUTS PRLLEL OUTPUTS SERIL OUTPUTS CP EO STR D O 0 O n O S O S L X X Z Z O 10 nc Fig.4 One D-latch. L X X Z Z nc O 11 H L X nc nc O 10 nc H H L Z O n 1 O 10 nc H H H L O n 1 O 10 nc H H H nc nc nc O 11 Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. = positive-going transition 5. = negative-going transition 6. Z = high impedance OFF state 7. nc = no change 8. O 11 = the information in the twelfth shift register stage. t the positive clock edge the information in the 10 th register stage is transferred to the 11 th register stage and the O s output. January

4 DC CHRCTERISTICS V SS =0 V. T amb ( C) PRMETER SYMBOL UNIT CONDITIONS MIN. MX. MIN. MX. MIN. MX. output voltage 5 V OL V V I =V SS or ; LOW; O n I o < 20 m output leakage 5 I OZH µ V o = 15 V current; HIGH; O n C CHRCTERISTICS V SS = 0 V; T amb =25 C; input transition times 20 ns. PRMETER TYPICL FORMUL FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where: dissipation per package f i + (f o C L ) V 2 DD R load = (P) f i + (f o C L ) V 2 DD f i = input frequency (MHz), f o = output frequency (MHz), C L = load capacitance (pf), (f o C L ) = sum of outputs = supply voltage C CHRCTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns. PRMETER SYMBOL TYP. MX. UNIT TYPICL EXTRPOLTION FORMUL Propagation delay ns + (0.55 ns/pf) C L CP to O s 10 t PHL ns 53 ns + (0.23 ns/pf) C L HIGH to LOW ns + (0.16 ns/pf) C L Propagation delay ns + (0.55 ns/pf) C L CP to O s 10 t PLH ns 44 ns + (0.23 ns/pf) C L LOW to HIGH ns + (0.16 ns/pf) C L Propagation delay ns + (0.55 ns/pf) C L CP to O s 10 t PHL ns 39 ns + (0.23 ns/pf) C L HIGH to LOW ns + (0.16 ns/pf) C L Propagation delay ns + (0.55 ns/pf) C L CP to O s 10 t PLH ns 49 ns + (0.23 ns/pf) C L LOW to HIGH ns + (0.16 ns/pf) C L January

5 PRMETER SYMBOL TYP. MX. UNIT TYPICL EXTRPOLTION FORMUL Propagation delay CP to O n 10 t PZL ns see note 1 OFF to LOW Propagation delay CP to O n 10 t PLZ ns see note 1 LOW to OFF Propagation delay STR to O n 10 t PZL ns see note 1 OFF to LOW Propagation delay STR to O n 10 t PLZ ns see note 1 LOW to OFF Output transition ns + (1.0 ns/pf) C L time; O s,o s 10 t THL ns 19 ns + (0.42 ns/pf) C L HIGH to LOW ns + (0.28 ns/pf) C L Output transition ns + (1.0 ns/pf) C L time; O s,o s 10 t TLH ns 19 ns + (0.42 ns/pf) C L LOW to HIGH ns + (0.28 ns/pf) C L Note 1. Definition of symbol equivalent to 3-state outputs. C CHRCTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns. PRMETER SYMBOL MIN. TYP. MX. UNIT output enable time 5 t PZL ns EO to O n OFF to LOW output disable time 5 t PLZ ns EO to O n LOW to OFF minimum clock pulse width 5 t WCPL ns LOW minimum strobe pulse width 5 t WSTRH ns HIGH January

6 PRMETER SYMBOL MIN. TYP. MX. UNIT set-up time 5 t su ns D to CP hold time 5 t hold 5 15 ns D to CP Maximum clock pulse frequency 5 f max 5 10 MHz Fig.5 Timing diagram. January

7 PPLICTION INFORMTION n example of applications for the is: Serial-to-parallel converting LED driver Fig.6 LED driver register. January

8 PDF: 1999 pr 16 Philips Semiconductors Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 D M E seating plane 2 L 1 Z 20 e b b 1 11 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT146-1 SC

9 PDF: 1999 pr 16 Philips Semiconductors Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L L p θ 1 e b p 10 w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT E04 MS-013C

DATA SHEET. HEF4027B flip-flops Dual JK flip-flop. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4027B flip-flops Dual JK flip-flop. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,