8-bit binary counter with output register; 3-state

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1 Rev pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7. The is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register. Counter and register have independent clock inputs Counter has master reset Complies with JEDEC standard no. 7 Multiple package options ESD protection: HBM JESD22-4E exceeds 2000 V MM JESD22-5- exceeds 200 V CDM JESD22-C0C exceeds 2000 V Specified from 40 C to+85 C and from 40 C to +25 C Table. Ordering information Type number Package Temperature range Name Description Version N 40 C to +25 C DIP6 plastic dual in-line package; 6 leads (300 mil) SOT38-4 D 40 C to +25 C SO6 plastic small outline package; 6 leads; body width 3.9 mm SOT09- PW 40 C to +25 C TSSOP6 plastic thin shrink small outline package; 6 leads; body width 4.4 mm SOT403- BQ 40 C to +25 C DHVQFN6 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 6 terminals; body mm SOT763-

2 4. Functional diagram 2 CE 0 CPC MRC 8-BIT BINRY COUNTER 3 CPR 8-BIT STORGE REGISTER RCO 9 Q0 5 Q Q2 2 4 OE 3-STTE OUTPUTS Q3 Q4 3 4 Q5 5 Q6 6 Q7 7 00aac542 Fig. Functional diagram 2 CE 3 CPC CPR RCO 9 Q0 5 Q Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 MRC OE aac544 4 OE 3 CPR 2 CE CPC 0 MRC EN3 C2 G CTR8 + (CT=255)Z4 CT=0 D 2D 3 2D 3 9 RCO 5 Q0 Q 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 00aac545 Fig 2. Logic symbol Fig 3. IEC logic symbol _2 Product data sheet Rev pril of 2

3 OE 4 CPR 3 CE 2 CPC 9 RCO MRC 0 R T R C S 5 Q0 R T R C S Q R T R C S 2 Q2 R T R C S 3 Q3 R T R C S 4 Q4 R T R C S 5 Q5 R T R C S 6 Q6 R T R C S 7 Q7 00aac543 Fig 4. Logic diagram _2 Product data sheet Rev pril of 2

4 5. Pinning information 5. Pinning Q Q2 Q3 Q4 Q5 Q6 Q7 GND aaj V CC Q0 OE CPR CE CPC MRC RCO Q Q2 Q3 Q4 Q5 Q6 Q7 GND 00aac564 Fig 5. Pin configuration DIP6 Fig 6. Pin configuration SO6 and TSSOP V CC 5 Q0 4 OE 3 CPR 2 CE CPC 0 MRC 9 RCO terminal index area Fig 7. Q2 Q3 Q4 Q5 Q6 Q7 Q 6 GND () 7 0 GND VCC RCO Transparent top view 00aac547 () The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Pin configuration DHVQFN6 Q0 OE CPR CE CPC MRC 5.2 Pin description Table 2. Pin description Symbol Pin Description Q0 to Q7 5,, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) RCO 9 ripple carry output (active LOW) MRC 0 master reset counter input (active LOW) CPC counter clock input (active HIGH) CE 2 count enable input (active LOW) CPR 3 register clock input (active HIGH) OE 4 output enable input (active LOW) V CC 6 supply voltage _2 Product data sheet Rev pril of 2

5 6. Functional description Table 3. Function table [] [2] Inputs Description OE CPR MRC CE CPC H X X X X Q outputs disable L X X X X Q outputs enable X X X X counter data stored into register X X X X register stage is not changed X X L X X counter clear X X H L advance one count X X H L no count X X H H X no count [] H = HIGH voltage level; L = LOW voltage level; X = don t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition. [2] RCO = Q0 Q Q2 Q3 Q4 Q5 Q6 Q7 (Q0 to Q7 are internal outputs of the counter). _2 Product data sheet Rev pril of 2

6 CPC CPR MRC CE OE Q0 Q Q2 Q3 Q4 Q5 Q6 Q7 RCO count inhibit counter clear high-impedance OFF-state 00aac548 Fig 8. Typical timing sequence _2 Product data sheet Rev pril of 2

7 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V [] - ±20 m I OK output clamping current V O < 0.5 V or V O >V CC V [] - ±20 m I O output current V O = 0.5 V to V CC V RCO standard output - ±25 m Qn bus driver output - ±35 m I CC supply current - 70 m I GND ground current 70 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +25 C [2] DIP6 package mw SO6 package mw TSSOP6 package mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP6 package: P tot derates linearly with 2 mw/k above 70 C. For SO6 packages: P tot derates linearly with 8 mw/k above 70 C. For TSSOP6 packages: P tot derates linearly with 5.5 mw/k above 60 C. For DHVQFN6 packages: P tot derates linearly with 8 mw/k above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t/ V input transition rise and fall rate V CC = 2.0 V ns/v V CC = 4.5 V ns/v V CC = 6.0 V ns/v T amb ambient temperature C _2 Product data sheet Rev pril of 2

8 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit V IH V IL V OH V OL I I I OZ HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current OFF-state output current Min Typ Max Min Max Min Max V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V I =V IH or V IL all outputs I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V RCO standard output I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V Qn bus driver output I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V V I =V IH or V IL all outputs I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V RCO standard output I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V Qn bus driver output I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V V I =V CC or GND; V CC = 6.0 V per pin; V I =V IH or V IL ; V O =V CC or GND; other inputs at V CC or GND; V CC = 6.0 V I CC supply current V I =V CC or GND; I O =0; V CC = 6.0 V C I input capacitance - - ±0. - ±.0 - ±.0 µ - - ±0.5 - ±5.0 - ±0 µ µ pf _2 Product data sheet Rev pril of 2

9 0. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit _2 Min Typ Max Min Max Min Max t pd propagation CPC to RCO; see Figure 9 [] delay V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns CPR to Qn; see Figure 0 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PLH LOW to HIGH MRC to RCO; see Figure propagation V CC = 2.0 V ns delay V CC = 4.5 V ns V CC = 6.0 V ns t en enable time OE to Qn; see Figure 2 [2] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t dis disable time OE to Qn; see Figure 2 [3] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width CPC and CPR; HIGH or LOW; see Figure 9 and Figure 0 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns MRC; LOW; see Figure V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time CPC to CPR; see Figure 4 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns CE to CPC; see Figure 3 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev pril of 2

10 Table 7. Dynamic characteristics continued GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit t h hold time CE to CPC; see Figure 3 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rec recovery time MRC to CPC; see Figure V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max C PD maximum frequency power dissipation capacitance CPC or CPR; see Figure 9 and Figure 0 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz V I = GND to V CC [4] pf [] t pd is the same as t PHL, t PLH. [2] t en is the same as t PZH and t PZL. [3] t dis is the same as t PLZ and t PHZ. [4] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Min Typ Max Min Max Min Max _2 Product data sheet Rev pril of 2

11 . Waveforms /f max V I CPC input RCO output GND V OH V OL t PHL t W t PLH 00aac550 Fig 9. Measurement points are given in Table 8. V OL and V OH are the typical output voltage levels that occur with the output load. Waveforms showing the propagation delays from the counter clock input (CPC) to ripple carry (RCO) output and the CPC pulse width Table 8. Measurement points Type Input Output V I V CC 0.5V CC 0.5V CC V I /f max CPR input Qn output GND V OH V OL t PLH t W t PHL 00aac549 Fig 0. Measurement points are given in Table 8. V OL and V OH are the typical output voltage levels that occur with the output load. Waveforms showing the propagation delays from the register clock input (CPR) to output (Qn) and the register clock pulse width _2 Product data sheet Rev pril 2009 of 2

12 t W V I MRC input GND t PLH V OH RCO output V OL V I t rec CPC input GND 00aac55 Fig. Measurement points are given in Table 8. V OL and V OH are the typical output voltage levels that occur with the output load. Waveforms showing the propagation delays from the master reset counter input (MRC) to output (RCO), the MRC pulse width and recovery time OE input V I GND V CC output LOW-to-OFF OFF-to-LOW V OL t PLZ 0 % t PZL output V OH HIGH-to-OFF OFF-to-HIGH GND t PHZ outputs enabled 90 % outputs disabled t PZH outputs enabled 00aac554 Fig 2. Measurement points are given in Table 8. V OL and V OH are the typical output voltage levels that occur with the output load. Waveforms showing the 3-state enable and disable times _2 Product data sheet Rev pril of 2

13 V I CE input GND t su t h t su t h V OH CPC input V OL 00aac553 Fig 3. Measurement points are given in Table 8. V OL and V OH are the typical output voltage levels that occur with the output load. Waveforms showing the set-up and hold times for the count enable input (CE) to the counter clock input (CPC) V I CPC input GND t su t h V OH CPR input V OL 00aac552 Fig 4. Measurement points are given in Table 8. V OL and V OH are the typical output voltage levels that occur with the output load. Waveforms showing the set-up and hold times for the counter clock input (CPC) to the register clock input (CPR) _2 Product data sheet Rev pril of 2

14 V I negative pulse 0 V 90 % 0 % t W t f t r t r t f V I positive pulse 0 V 0 % 90 % t W V CC V CC G VI DUT VO RL S open RT CL 00aad983 Fig 5. Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S = Test selection switch. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load Switch position V CC V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 2.0 V to 6.0 V V CC 6 ns 50 pf kω open GND V CC _2 Product data sheet Rev pril of 2

15 2. Package outline DIP6: plastic dual in-line package; 6 leads (300 mil) SOT38-4 D M E seating plane 2 L Z 6 e b b 9 b 2 w M c (e ) M H pin index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT 2 () () () max. b b 2 c D E e L M Z min. max. b e M E H w max mm inches Note. Plastic or metal protrusions of 0.25 mm (0.0 inch) maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT Fig 6. Package outline SOT38-4 (DIP6) _2 Product data sheet Rev pril of 2

16 SO6: plastic small outline package; 6 leads; body width 3.9 mm SOT09- D E X c y H E v M Z 6 9 Q 2 ( ) 3 pin index θ L p 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT09-076E07 MS Fig 7. Package outline SOT09- (SO6) _2 Product data sheet Rev pril of 2

17 TSSOP6: plastic thin shrink small outline package; 6 leads; body width 4.4 mm SOT403- D E X c y H E v M Z 6 9 pin index 2 Q ( ) 3 θ 8 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT403- MO-53 EUROPEN PROJECTION ISSUE DTE Fig 8. Package outline SOT403- (TSSOP6) _2 Product data sheet Rev pril of 2

18 DHVQFN6: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 6 terminals; body 2.5 x 3.5 x 0.85 mm SOT763- D B E c terminal index area detail X terminal index area e e b 2 7 v M w M C C B y C C y L 8 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 9. Package outline SOT763- (DHVQFN6) _2 Product data sheet Rev pril of 2

19 3. bbreviations Table 0. cronym CDM CMOS DUT ESD HBM MM TTL bbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes _ Product data sheet - _ Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Quick reference data incorporated in to Section 9 and Section 0. dded type number N (DIP6 package) _ Product data sheet - - _2 Product data sheet Rev pril of 2

20 5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 5.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com _2 Product data sheet Rev pril of 2

21 7. Contents General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 28 pril 2009 Document identifier: _2

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