In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

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Kellie Lane
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1 Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, ogic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of or use Instead of sales.addresses@ or sales.addresses@ use salesaddresses@nexperia.com ( ) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - NXP N.V. (year). All rights reserved or Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

2 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines Octal D-type flip-flop; positive edge-trigger; File under Integrated Circuits, IC06 December 1990

3 Octal D-type flip-flop; positive edge-trigger; FEATURES non-inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common output enable input Independent register and buffer operation Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the OW-to-IG CP transition. When OE is OW, the contents of the 8 flip-flops are available at the outputs. When OE is IG, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 374 is functionally identical to the 34, but has non-inverting outputs. QUICK REFERENCE DATA GND = 0 V; T amb =2 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay CP to Q n C = 1 pf; V CC = V 1 13 ns f max maximum clock frequency Mz C I input capacitance pf C PD power dissipation capacitance per flip-flop notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1. V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December

4 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 OE output enable input (active OW) 2,, 6, 9, 12, 1, 16, 19 Q 0 to Q 7 flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D 0 to D 7 data inputs 10 GND ground (0 V) 11 CP clock input (OW-to-IG, edge-triggered) 20 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December

5 FUNCTION TABE OPERATING MODES load and read register load register and disable outputs INPUTS INTERNA OUTPUTS OE CP D n FIP-FOPS Q 0 to Q 7 l h l h Z Z Notes 1. = IG voltage level h = IG voltage level one set-up time prior to the OW-to-IG CP transition = OW voltage level I = OW voltage level one set-up time prior to the OW-to-IG CP transition Z = high impedance OFF-state = OW-to-IG CP transition Fig.4 Functional diagram. Fig. ogic diagram. December

6 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C =0pF SYMBO t P / t P t PZ / t PZ t PZ / t PZ PARAMETER propagation delay 0 CP to Q n output enable time OE to Q n output disable time 0 OE to Q n t T / t T output transition time 14 4 t W t su t h f max clock pulse width IG or OW set-up time D n to CP hold time D n to CP maximum clock pulse frequency T amb ( C) 74C to to +12 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) Mz WAVEFORMS Fig.7 Fig.7 Fig.8 Fig.8 December 1990

7 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE CP D n UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C =0pF T amb ( C) TEST CONDITIONS ns ns 4. Fig ns 4. Fig.7 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +12 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay CP to Q n t PZ / t PZ output enable time OE to Q n t PZ / t PZ output disable time OE to Q n t T / t T output transition time ns 4. t W t su t h f max clock pulse width IG or OW set-up time D n to CP hold time D n to CP maximum clock pulse frequency ns ns 4. Fig.8 3 ns 4. Fig Mz 4. December

8 AC WAVEFORMS (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Waveforms showing the clock (CP) to output (Q n ) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for D n input. December

9 PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Important notice Dear Customer, On 7 February 27 the former NP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, ogic and