DATA SHEET. HEF4514B MSI 1-of-16 decoder/demultiplexer with input latches. For a complete data sheet, please also download: INTEGRATED CIRCUITS

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1 INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC 1-of-16 decoder/demultiplexer with input latches File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs ( 0 to 3 ), a latch enable input (EL), and an active LOW enable input (E). The 16 outputs (O 0 to O 15 ) are mutually exclusive active HIGH. When EL is HIGH, the selected output is determined by the data on n. When EL goes LOW, the last data present at n are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is HIGH. t E HIGH, all outputs are LOW. The enable input (E) does not affect the state of the latch. When the is used as a demultiplexer, E is the data input and 0 to 3 are the address inputs. Fig.1 Functional diagram. P(N): 24-lead DIL; plastic (SOT101-1) D(F): 24-lead DIL; ceramic (cerdip) (SOT94) T(D): 24-lead SO; plastic (SOT137-1) ( ): Package Designator North merica Fig.2 Pinning diagram. PPLICTION INFORMTION PINNING 0 to 3 E EL O 0 to O 15 address inputs enable input (active LOW) latch enable input outputs (active HIGH) Some examples of applications for the are: Digital multiplexing. ddress decoding. Hexadecimal/BCD decoding. FMILY DT, I DD LIMITS category See Family Specifications January

3 Fig.3 Logic diagram. Fig.4 Logic diagram (one latch). January

4 TRUTH TBLE INPUTS OUTPUTS E O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 O 8 O 9 O 10 O 11 O 12 O 13 O 14 O 15 H X X X X L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L H L L L L H L L L L L L L L L L L L L L L L H L L L L H L L L L L L L L L L L L L L H H L L L L L H L L L L L L L L L L L L L L L H L L L L L H L L L L L L L L L L L L H L H L L L L L L H L L L L L L L L L L L L H H L L L L L L L H L L L L L L L L L L H H H L L L L L L L L H L L L L L L L L L L L L H L L L L L L L L H L L L L L L L L H L L H L L L L L L L L L H L L L L L L L L H L H L L L L L L L L L L H L L L L L L H H L H L L L L L L L L L L L H L L L L L L L H H L L L L L L L L L L L L H L L L L H L H H L L L L L L L L L L L L L H L L L L H H H L L L L L L L L L L L L L L H L L H H H H L L L L L L L L L L L L L L L H Notes 1. EL = HIGH; H = HIGH state (the more positive voltage); L = LOW state (the less positive voltage); X = state is immaterial C CHRCTERISTICS V SS =0V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL TYP. MX. TYPICL EXTRPOLTION FORMUL Propagation delays n,el O n ns 233 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 84 ns + (0,23 ns/pf) C L ns 57 ns + (0,16 ns/pf) C L ns 243 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 84 ns + (0,23 ns/pf) C L ns 57 ns + (0,16 ns/pf) C L E O n ns 148 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 54 ns + (0,23 ns/pf) C L ns 37 ns + (0,16 ns/pf) C L ns 173 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 59 ns + (0,23 ns/pf) C L ns 42 ns + (0,16 ns/pf) C L January

5 C CHRCTERISTICS V SS =0V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MX. TYPICL EXTRPOLTION FORMUL Output transition ns 40 ns + (1,0 ns/pf) C L times 10 t THL ns 14 ns + (0,42 ns/pf) C L HIGH to LOW ns 11 ns + (0,28 ns/pf) C L ns 35 ns + (1,0 ns/pf) C L LOW to HIGH 10 t TLH ns 14 ns + (0,42 ns/pf) C L ns 11 ns + (0,28 ns/pf) C L Set-up time ns n EL 10 t su ns ns Hold time ns n EL 10 t hold 0 20 ns ns Minimum EL pulse ns width; HIGH 10 t WELH ns ns see also waveforms Fig.5 V DD V TYPICL FORMUL FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) January

6 Fig.5 Waveforms showing minimum pulse width for EL, set-up and hold times for n to EL. Set-up and hold times are shown as positive values but may be specified as negative values. January

7 Package information Package outlines SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L L p θ 1 e b p 12 w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT E05 MS-013D January

8 Package information Package outlines DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 seating plane D 2 M E L 1 Z 24 e b b 1 13 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w Z (1) max Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT G02 MO-015D January

DATA SHEET. HEF4027B flip-flops Dual JK flip-flop. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4027B flip-flops Dual JK flip-flop. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,