Dual 2-to-4 line decoder/demultiplexer
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1 74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9. The 74LV9 is a dual -to-4 line decoder/demultiplexer. It has two independent decoders, each accepting two binary weighted inputs (n0 and n) and providing four mutually exclusive outputs (ny0 to ny) that are LOW when selected. Each decoder has an active LOW input (ne). When ne is HIGH, every output is forced HIGH. The enable input can be used as the data input for a -to-4 demultiplexer application. Wide operating voltage:.0 V to 5.5 V Optimized for low voltage applications:.0 V to.6 V ccepts TTL input levels between V CC =.7 V and V CC =.6 V Typical output ground bounce < 0.8 V at V CC =. V and T amb = 5 C Typical HIGH-level output voltage (V OH ) undershoot: > V at V CC =. V and T amb =5 C Demultiplexing capability Two independent -to-4 line decoders Multifunction capability ctive LOW mutually exclusive outputs ESD protection: HBM JESD-4E exceeds 000 V MM JESD-5- exceeds 00 V Multiple package options Specified from 40 C to+85 C and from 40 C to +5 C Table. Type number Ordering information Package Temperature range Name Description Version 74LV9N 40 C to +5 C DIP6 plastic dual in-line package; 6 leads (00 mil) SOT8-4 74LV9D 40 C to +5 C SO6 plastic small outline package; 6 leads; body width.9 mm SOT09-
2 74LV9 Table. Type number Ordering information continued Package 74LV9DB 40 C to +5 C SSOP6 plastic shrink small outline package; 6 leads; body width 5. mm 74LV9PW 40 C to +5 C TSSOP6 plastic thin shrink small outline package; 6 leads; body width 4.4 mm 74LV9BQ 40 C to +5 C DHVQFN6 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 6 terminals; body mm 4. Functional diagram Temperature range Name Description Version SOT8- SOT40- SOT E E Y0 Y Y Y Y0 Y Y Y DX G 0 DX G X/Y EN X/Y EN mna779 (a) (b) mna78 a) demultiplexer b) decoder Fig. Logic symbol Fig. IEC logic symbol 0 DECODER Y0 Y Y Y 7 E 4 0 DECODER Y0 Y Y 0 Y 9 5 E mna780 Fig. Functional diagram 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December 007 of 6
3 74LV9 5. Pinning information 5. Pinning 74LV9 E V CC E 0 terminal index area 0 E VCC E 0 Y0 Y Y Y0 Y Y0 Y Y Y V () CC 7 0 Y0 Y Y Y 7 0 Y 8 9 GND 8 9 Y GND Y 00aah07 00aad09 Transparent top view () The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP6, SO6 and (T)SSOP6 Fig 5. Pin configuration DHVQFN6 5. Pin description Table. Pin description Symbol Pin Description E enable input (active LOW) 0 address input address input Y0 4 output Y 5 output Y 6 output Y 7 output GND 8 ground (0 V) Y 9 output Y 0 output Y output Y0 output 0 4 address input address input E 5 enable input (active LOW) V CC 6 supply voltage 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December 007 of 6
4 74LV9 6. Functional description Table. Function table H = HIGH voltage level; L = LOW voltage level; X = don t care Input Output ne n0 n ny0 ny ny ny H X X H H H H L L L L H H H L H L H L H H L L H H H L H L H H H H H L 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 604). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V [] - ±0 m I OK output clamping current V O < 0.5 V or V O >V CC V [] - ±50 m I O output current V O = 0.5 V to (V CC V) - ±5 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +5 C DIP6 package [] mw SO6 package [] mw (T)SSOP6 package [4] mw DHVQFN6 package [5] mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [] P tot derates linearly with mw/k above 70 C. [] P tot derates linearly with 8 mw/k above 70 C. [4] P tot derates linearly with 5.5 mw/k above 60 C. [5] P tot derates linearly with 4.5 mw/k above 60 C. 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
5 74LV9 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage [] V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t/ V input transition rise and fall rate V CC =.0 V to.0 V ns/v V CC =.0 V to.7 V ns/v V CC =.7 V to.6 V ns/v V CC =.6 V to 5.5 V ns/v [] The static characteristics are guaranteed from V CC =. V to V CC = 5.5 V, but LV devices are guaranteed to function down to V CC =.0 V (with input levels GND or V CC ). 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +5 C Unit Min Typ [] Max Min Max V IH HIGH-level input voltage V CC =. V V V CC =.0 V V V CC =.7 V to.6 V V V CC = 4.5 V to 5.5 V 0.7V CC V CC - V V IL LOW-level input voltage V CC =. V V V CC =.0 V V V CC =.7 V to.6 V V V CC = 4.5 V to 5.5 V V CC - 0.V CC V V OH HIGH-level output voltage V I = V IH or V IL I O = 00 µ; V CC =. V V I O = 00 µ; V CC =.0 V V I O = 00 µ; V CC =.7 V V I O = 00 µ; V CC =.0 V V I O = 00 µ; V CC = 4.5 V V I O = 6 m; V CC =.0 V V I O = m; V CC = 4.5 V V 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
6 74LV9 Table 6. Static characteristics continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +5 C Unit V OL LOW-level output voltage V I = V IH or V IL I O = 00 µ; V CC =. V V I O = 00 µ; V CC =.0 V V I O = 00 µ; V CC =.7 V V I O = 00 µ; V CC =.0 V V I O = 00 µ; V CC = 4.5 V V I O = 6 m; V CC =.0 V V I O = m; V CC = 4.5 V V I I input leakage current V I =V CC or GND; µ V CC = 5.5 V I CC supply current V I = V CC or GND; I O = 0 ; µ V CC = 5.5 V I CC additional supply current per input; V I = V CC 0.6 V; µ V CC =.7 V to.6 V C I input capacitance pf [] Typical values are measured at T amb = 5 C. 0. Dynamic characteristics Min Typ [] Max Min Max Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 8. Symbol Parameter Conditions 40 C to +85 C 40 C to +5 C Unit Min Typ [] Max Min Max t pd propagation delay nn to nyn; see Figure 6 [] V CC =. V ns V CC =.0 V ns V CC =.7 V ns V CC =.0 V to.6 V; C L =5pF [] ns V CC =.0 V to.6 V [] ns V CC = 4.5 V to 5.5 V ns nen to Yn; see Figure 7 V CC =. V ns V CC =.0 V ns V CC =.7 V ns V CC =.0 V to.6 V; C L =5pF [] ns V CC =.0 V to.6 V [] ns V CC = 4.5 V to 5.5 V ns 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
7 74LV9 Table 7. Dynamic characteristics continued GND = 0 V; For test circuit see Figure 8. Symbol Parameter Conditions 40 C to +85 C 40 C to +5 C Unit Min Typ [] Max Min Max [4] pf C PD power dissipation capacitance C L = 50 pf; f i = MHz; V I = GND to V CC [] ll typical values are measured at T amb =5 C. [] t pd is the same as t PLH and t PHL. [] Typical values are measured at nominal supply voltage (V CC =. V). [4] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V CC f i N+Σ(C L V CC f o ) where: f i = input frequency in MHz, f o = output frequency in MHz C L = output load capacitance in pf V CC = supply voltage in V N = number of inputs switching Σ(C L V CC f o ) = sum of the outputs.. Waveforms V I V I nn input V M ne input V M GND GND t PHL t PLH t PHL t PLH V OH V OH nyn output V M nyn output V M V OL mna78 V OL mna78 Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Fig 6. Input (nn) to output (nyn) propagation delays Fig 7. Enable input (ne) to output (nyn) propagation delays Table 8. Measurement points Supply voltage Input Output V CC V M V M <.7 V 0.5V CC 0.5V CC.7 V to.6 V.5 V.5 V 4.5 V 0.5V CC 0.5V CC 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
8 74LV9 V CC PULSE GENERTOR V I R T D.U.T. V O C L 50 pf R L kω 00aaa66 Fig 8. Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. R L = Load resistance. C L = Load capacitance including jig and probe capacitance. Load circuit for switching times Table 9. Test data Supply voltage Input V CC V I t r, t f <.7 V V CC.5 ns.7 V to.6 V.7 V.5 ns 4.5 V V CC.5 ns 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
9 74LV9. Package outline DIP6: plastic dual in-line package; 6 leads (00 mil) SOT8-4 D M E seating plane L Z 6 e b b 9 b w M c (e ) M H pin index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT () () () max. b b c D E e L M Z min. max. b e M E H w max mm inches Note. Plastic or metal protrusions of 0.5 mm (0.0 inch) maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT Fig 9. Package outline SOT8-4 (DIP6) 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
10 74LV9 SO6: plastic small outline package; 6 leads; body width.9 mm SOT09- D E X c y H E v M Z 6 9 Q ( ) pin index θ L p 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max..75 b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT09-076E07 MS Fig 0. Package outline SOT09- (SO6) 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
11 74LV9 SSOP6: plastic shrink small outline package; 6 leads; body width 5. mm SOT8- D E X c y H E v M Z 6 9 Q ( ) pin index 8 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D () E () e H E L L p Q v w y Z() max. mm θ o 8 o 0 Note. Plastic or metal protrusions of 0.5 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT8- MO Fig. Package outline SOT8- (SSOP6) 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December 007 of 6
12 74LV9 TSSOP6: plastic thin shrink small outline package; 6 leads; body width 4.4 mm SOT40- D E X c y H E v M Z 6 9 pin index Q ( ) θ 8 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D () E () e H () E L L p Q v w y Z max. mm θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included.. Plastic interlead protrusions of 0.5 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT40- MO-5 EUROPEN PROJECTION ISSUE DTE Fig. Package outline SOT40- (TSSOP6) 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December 007 of 6
13 74LV9 DHVQFN6: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 6 terminals; body.5 x.5 x 0.85 mm SOT76- D B E c terminal index area detail X terminal index area e e b 7 v M w M C C B y C C y L 8 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig. Package outline SOT76- (DHVQFN6) 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December 007 of 6
14 74LV9. bbreviations Table 0. cronym CMOS DUT ESD HBM MM TTL bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV9_4 007 Product data sheet - 74LV9_ Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section : DHVQFN6 package added. Section 7: derating values added for DHVQFN6 package. Section : outline drawing added for DHVQFN6 package. 74LV9_ 000 Product specification - 74LV9_ 74LV9_ Product specification - 74LV9_ 74LV9_ 9970 Product specification LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
15 74LV9 5. Legal information 5. Data sheet status Document status [][] Product status [] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [] The term short data sheet is explained in section Definitions. [] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL 5. Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 5. Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 604) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For additional information, please visit: For sales office addresses, send an to: salesaddresses@nxp.com 74LV9_4 NXP B.V ll rights reserved. Product data sheet Rev. 04 December of 6
16 74LV9 7. Contents General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V ll rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: December 007 Document identifier: 74LV9_4
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More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 07 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and
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Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
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Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
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Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
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Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input
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Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
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Rev. 6 3 ugust 0 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC standard
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Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
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Rev. 04 17 March 2009 Product data sheet 1. General description The is a for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH
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Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
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Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.
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Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in
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Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
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Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features
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Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.
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Rev. 7 pril 203 Product data sheet. General description The consists of four non-inverting buffers/line drivers with 3-state outputs (ny) that are controlled by the output enable input (noe). HIGH at noe
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