The 74LV08 provides a quad 2-input AND function.

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1 Quad 2-input ND gate Rev pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0 and 74HCT0. The provides a quad 2-input ND function. Wide operating voltage:.0 V to 5.5 V Optimized for low voltage applications:.0 V to 3.6 V ccepts TTL input levels between V CC = 2.7 V and V CC = 3.6 V Typical output ground bounce < 0. V at V CC = 3.3 V and T amb = 25 C Typical HIGH-level output voltage (V OH ) undershoot: > 2 V at V CC = 3.3 V and T amb =25 C ESD protection: HBM JESD22-4E exceeds 2000 V MM JESD22-5- exceeds 200 V Multiple package options Specified from 40 C to+5 C and from 40 C to +25 C Table. Type number Ordering information Package Temperature range Name Description Version N 40 C to +25 C DIP4 plastic dual in-line package; 4 leads (300 mil) SOT27- D 40 C to +25 C SO4 plastic small outline package; 4 leads; SOT0- body width 3.9 mm DB 40 C to +25 C SSOP4 plastic shrink small outline package; 4 leads; SOT337- body width 5.3 mm PW 40 C to +25 C TSSOP4 plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402-

2 Quad 2-input ND gate 4. Functional diagram 2 & B 2 2B Y 2Y & B 4 4B 3Y 4Y mna & & B Y mna22 mna223 Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5. Pinning 4 V CC B Y B 4 B 2 4 V CC 3 4B 2 2B Y 3B Y 2 2B Y 3B 2Y GND Y 2Y GND Y 00aaj959 00aaj960 Fig 4. Pin configuration DIP4, SO4 Fig 5. Pin configuration (T)SSOP4 _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

3 Quad 2-input ND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description, 2, 3, 4, 4, 9, 2 data input B, 2B, 3B, 4B 2, 5, 0, 3 data input Y, 2Y, 3Y, 4Y 3, 6,, data output GND 7 ground (0 V) V CC 4 supply voltage 6. Functional description Table 3. Function selection [] Input Output n nb ny L X L X L L H H H [] H = HIGH voltage level; L = LOW voltage level; X = don t care 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V [] - ±20 m I OK output clamping current V O < 0.5 V or V O >V CC V [] - ±50 m I O output current V O = 0.5 V to (V CC V) - ±25 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +25 C [2] DIP4 package mw SO4, SSOP4, TSSOP4-500 mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP4 packages: above 70 C the value of P tot derates linearly with 2 mw/k. For SO4 packages: above 70 C the value of P tot derates linearly with mw/k. For (T)SSOP4 packages: above 60 C the value of P tot derates linearly with 5.5 mw/k. _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

4 Quad 2-input ND gate. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage [] V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t/ V input transition rise and fall rate V CC =.0 V to 2.0 V ns/v V CC = 2.0 V to 2.7 V ns/v V CC = 2.7 V to 3.6 V ns/v V CC = 3.6 V to 5.5 V ns/v [] The static characteristics are guaranteed from V CC =.2 V to V CC = 5.5 V, but LV devices are guaranteed to function down to V CC =.0 V (with input levels GND or V CC ). 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +5 C 40 C to +25 C Unit Min Typ [] Max Min Max V IH HIGH-level input voltage V CC =.2 V V V CC = 2.0 V V V CC = 2.7 V to 3.6 V V V CC = 4.5 V to 5.5 V 0.7V CC V CC - V V IL LOW-level input voltage V CC =.2 V V V CC = 2.0 V V V CC = 2.7 V to 3.6 V V V CC = 4.5 V to 5.5 V V CC - 0.3V CC V V OH HIGH-level output voltage V I = V IH or V IL I O = 00 µ; V CC =.2 V V I O = 00 µ; V CC = 2.0 V V I O = 00 µ; V CC = 2.7 V V I O = 00 µ; V CC = 3.0 V V I O = 00 µ; V CC = 4.5 V V I O = 6 m; V CC = 3.0 V V I O = 2 m; V CC = 4.5 V V _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

5 Quad 2-input ND gate Table 6. Static characteristics continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +5 C 40 C to +25 C Unit V OL LOW-level output voltage V I = V IH or V IL I O = 00 µ; V CC =.2 V V I O = 00 µ; V CC = 2.0 V V I O = 00 µ; V CC = 2.7 V V I O = 00 µ; V CC = 3.0 V V I O = 00 µ; V CC = 4.5 V V I O = 6 m; V CC = 3.0 V V I O = 2 m; V CC = 4.5 V V I I input leakage current V I =V CC or GND; V CC = 5.5 V µ I CC supply current V I = V CC or GND; I O = 0 ; µ V CC = 5.5 V I CC additional supply current per input; V I = V CC 0.6 V; µ V CC = 2.7 V to 3.6 V C I input capacitance pf [] Typical values are measured at T amb = 25 C. 0. Dynamic characteristics Min Typ [] Max Min Max Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter Conditions 40 C to +5 C 40 C to +25 C Unit Min Typ [] Max Min Max t pd propagation delay n, nb to ny; see Figure 6 [2] V CC =.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V; C L =5pF [3] ns V CC = 3.0 V to 3.6 V [3] ns V CC = 4.5 V to 5.5 V ns C PD power dissipation capacitance C L = 50 pf; f i = MHz; V I = GND to V CC [4] pf [] ll typical values are measured at T amb =25 C. [2] t pd is the same as t PLH and t PHL. [3] Typical values are measured at nominal supply voltage (V CC = 3.3 V). [4] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ(C L V 2 CC f o ) where: f i = input frequency in MHz, f o = output frequency in MHz C L = output load capacitance in pf V CC = supply voltage in Volts N = number of inputs switching Σ(C L V 2 CC f o ) = sum of the outputs. _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

6 Quad 2-input ND gate. Waveforms V I n, nb input V M GND t PHL t PLH V OH ny output V M V OL mna224 Fig 6. Measurement points are given in Table. V OL and V OH are typical voltage output levels that occur with the output load. The input (n, nb) to output (ny) propagation delays Table. Measurement points Supply voltage Input Output V CC V M V M < 2.7 V 0.5V CC 0.5V CC 2.7 V to 3.6 V.5 V.5 V 4.5 V 0.5V CC 0.5V CC V CC PULSE GENERTOR V I R T D.U.T. V O C L 50 pf R L kω 00aaa663 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. R L = Load resistance. C L = Load capacitance including jig and probe capacitance. Load circuit for switching times Table 9. Test data Supply voltage Input V CC V I t r, t f < 2.7 V V CC 2.5 ns 2.7 V to 3.6 V 2.7 V 2.5 ns 4.5 V V CC 2.5 ns _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

7 Quad 2-input ND gate 2. Package outline DIP4: plastic dual in-line package; 4 leads (300 mil) SOT27- D M E seating plane 2 L Z 4 e b b w M c (e ) M H pin index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 2 () () min. max. b b c D E e e L M E M H w () Z max Note. Plastic or metal protrusions of mm (0.0 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT27-050G04 MO-00 SC Fig. Package outline SOT27- (DIP4) _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

8 Quad 2-input ND gate SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT0- D E X c y H E v M Z 4 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT0-076E06 MS Fig 9. Package outline SOT0- (SO4) _3 NXP B.V ll rights reserved. Product data sheet Rev pril 2009 of 3

9 Quad 2-input ND gate SSOP4: plastic shrink small outline package; 4 leads; body width 5.3 mm SOT337- D E X c y H E v M Z 4 Q 2 ( ) 3 pin index 7 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E () e H E L L p Q v w y Z() max. mm θ o o 0 Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337- MO Fig 0. Package outline SOT337- (SSOP4) _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

10 Quad 2-input ND gate TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 pin index 2 Q ( ) 3 θ 7 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm θ o o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE Fig. Package outline SOT402- (TSSOP4) _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

11 Quad 2-input ND gate 3. bbreviations Table 0. cronym CMOS DUT ESD HBM MM TTL bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes _ Product data sheet - _2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name when appropriate. _ Product specification Product specification - - _3 NXP B.V ll rights reserved. Product data sheet Rev pril 2009 of 3

12 Quad 2-input ND gate 5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 5.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: For sales office addresses, please send an to: _3 NXP B.V ll rights reserved. Product data sheet Rev pril of 3

13 Quad 2-input ND gate 7. Contents General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V ll rights reserved. For more information, please visit: For sales office addresses, please send an to: Date of release: 6 pril 2009 Document identifier: _3