Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

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1 Rev June 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (SD) and (RD) inputs, and complementary and outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V MOS low power consumption Direct interface with TTL levels omplies with JEDE standard JESD-B/JESD36 ESD protection: HBM JESD22-114D exceeds 2000 V DM JESD exceeds 1000 V Specified from 40 to +5 and 40 to 125 Table 1. Type number Ordering information Package Temperature range Name Description Version D 40 to +125 SO14 plastic small outline package; 14 leads; SOT10-1 body width 3.9 mm DB 40 to +125 SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm PW 40 to +125 TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm B 40 to +125 DHVFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body mm SOT762-1

2 4. Functional diagram 4 1SD 2 1D D SD P P FF SD SD SD 1D 1 D 2D 2 1P P 2P FF 1 2 RD 1RD 2RD S 1 1D R S 1 1D R RD 10 2SD 12 2D 11 2P RD SD D P FF RD mna41 mna RD mna420 Fig 1. Logic symbol Fig 2. IE logic symbol Fig 3. Functional diagram D RD SD mna421 P Fig 4. Logic diagram for one flip-flop _6 Product data sheet Rev June of 16

3 5. Pinning information 5.1 Pinning 1RD 1 14 V terminal 1 index area 1RD V 1D RD 1D RD 1P D 1P D 1SD P 2SD 2 1SD GND (1) P 2SD 2 GND 7 2 GND 2 001aad aad106 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration for SO14 and (T)SSOP14 Fig 6. Pin configuration for DHVFN Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1P 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1 5 true output 1 6 complement output GND 7 ground (0 V) 2 complement output 2 9 true output 2SD 10 asynchronous set-direct input (active LOW) 2P 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) V 14 supply voltage _6 Product data sheet Rev June of 16

4 6. Functional description Table 3. Function table [1] Input Output nsd nrd np nd n n L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level L = LOW voltage level X = don t care Table 4. Function table [1] Input Output nsd nrd np nd n n+1 n n+1 H H L L H H H H H L [1] H = HIGH voltage level L = LOW voltage level = LOW-to-HIGH transition n+1 = state after the next LOW-to-HIGH P transition X = don t care 7. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IE 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions Min Max Unit V supply voltage V I IK input clamping current V I < 0 V 50 - m V I input voltage [1] V I OK output clamping current V O > V or V O < 0 V - ±50 m V O output voltage [2] 0.5 V V I O output current V O = 0 V to V - ±50 m I supply current m I GND ground current m T stg storage temperature P tot total power dissipation T amb = 40 to +125 [3] mw [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 the value of P tot derates linearly with mw/k. For (T)SSOP14 packages: above 60 the value of P tot derates linearly with 5.5 mw/k. For DHVFN14 packages: above 60 the value of P tot derates linearly with 4.5 mw/k. _6 Product data sheet Rev June of 16

5 . Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter onditions Min Typ Max Unit V supply voltage for maximum speed performance V for low-voltage applications V V I input voltage V V o output voltage 0 - V V T amb ambient temperature t/ V input transition rise and V = 1.2 V to 2.7 V 0-20 ns/v fall rate V = 2.7 V to 3.6 V 0-10 ns/v 9. Static characteristics Table 7. Static characteristics t recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions 40 to to +125 Unit V IH V IL V OH V OL I I I I I HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current supply current additional supply current input capacitance [1] ll typical values are measured at V = 3.3 V (unless stated otherwise) and T amb =25. Min Typ [1] Max Min Max V = 1.2 V V - - V - V V = 2.7 V to 3.6 V V V = 1.2 V V V = 2.7 V to 3.6 V V V I =V IH or V IL I O = 100 µ; V V V V = 2.7 V to 3.6 V I O = 12 m; V = 2.7 V V I O = 1 m; V = 3.0 V V I O = 24 m; V = 3.0 V V V I =V IH or V IL I O = 100 µ; V V = 2.7 V to 3.6 V I O = 12 m; V = 2.7 V V I O = 24 m; V = 3.0 V V V = 3.6 V; V I = 5.5 V or GND - ±0.1 ±5 - ±20 µ V = 3.6 V; V I =V or GND; I O = µ per input pin; V = 2.7 V to 3.6 V; V I =V 0.6 V; I O = µ V = 0 V to 3.6 V; pf V I = GND to V _6 Product data sheet Rev June of 16

6 10. Dynamic characteristics Table. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter onditions 40 to to +125 Unit Min Typ [1] Max Min Max t pd propagation np to n, n; see Figure 7 [2] delay V = 1.2 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns nsd to n, n; see Figure V = 1.2 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns nrd to n, n; see Figure V = 1.2 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns t W pulse width clock HIGH or LOW; see Figure 7 V = 2.7 V ns V = 3.0 V to 3.6 V ns set or reset LOW; see Figure V = 2.7 V ns V = 3.0 V to 3.6 V ns t rec recovery time set or reset; see Figure V = 2.7 V ns V = 3.0 V to 3.6 V ns t su set-up time nd to np; see Figure 7 V = 2.7 V ns V = 3.0 V to 3.6 V ns t h hold time nd to np; see Figure 7 V = 2.7 V ns V = 3.0 V to 3.6 V ns f max maximum np; see Figure 7 frequency V = 2.7 V MHz V = 3.0 V to 3.6 V MHz t sk(o) output skew time V = 3.0 V to 3.6 V [3] ns PD power per flip-flop; V I = GND to V [4] dissipation capacitance V = 3.3 V pf [1] Typical values are measured at T amb =25. For V = 3.0 V to 3.6 V range, typical values are measured at 3.3 V. [2] t pd is the same as t PLH and t PHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. _6 Product data sheet Rev June of 16

7 [4] PD is used to determine the dynamic power dissipation (P D in µw). P D = PD V 2 f i N+Σ( L V 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz L = output load capacitance in pf V = supply voltage in Volts N = number of inputs switching Σ( L V 2 f o ) = sum of the outputs 11. waveforms V I nd input GND t h t h t su 1/f max t su V I np input GND t W t PHL t PLH V OH n output V OL V OH n output V OL t PLH t PHL mna422 Fig 7. The shaded areas indicate when the input is permitted to change for predictable output performance. = 1.5 V at V 2.7 V; = 0.5 V at V < 2.7 V; V OL and V OH are typical output voltage levels that occur with the output load. The clock input (np) to output (n, n) propagation delays, the clock pulse width, the nd to np set-up, the np to nd hold times, and the maximum frequency _6 Product data sheet Rev June of 16

8 V I np input GND t rec V I nsd input GND V I t W t W nrd input GND t PLH t PHL V OH n output V OL V OH n output V OL t PHL t PLH mna423 Fig. = 1.5 V at V 2.7 V; = 0.5 V at V < 2.7 V; V OL and V OH are typical output voltage levels that occur with the output load. The set (nsd) and reset (nrd) input to output (n, n) propagation delays, the set and reset pulse widths, and the nrd to np recovery time _6 Product data sheet Rev June 2007 of 16

9 V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V PULSE GENERTOR V I DUT V O RT L RL 001aaf615 Fig 9. Test data is given in Table 9. Definitions for test circuit: R L = Load resistance. L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. Load circuitry for switching times Table 9. Test data Supply voltage Input Load V I t r, t f L R L 1.2 V V 2.5 ns 50 pf 500 Ω 2.7 V 2.7 V 2.5 ns 50 pf 500 Ω 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pf 500 Ω _6 Product data sheet Rev June of 16

10 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT10-1 D E X c y H E v M Z 14 pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o o OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT E06 MS Fig 10. Package outline SOT10-1 (SO14) _6 Product data sheet Rev June of 16

11 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z ( ) 3 pin 1 index 1 7 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p v w y Z(1) max. mm θ o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT337-1 MO Fig 11. Package outline SOT337-1 (SSOP14) _6 Product data sheet Rev June of 16

12 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 pin 1 index 2 1 ( ) 3 θ 1 7 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p v w y Z max. mm θ o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT SOT402-1 MO-153 EUROPEN PROJETION ISSUE DTE Fig 12. Package outline SOT402-1 (TSSOP14) _6 Product data sheet Rev June of 16

13 DHVFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.5 mm SOT762-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 6 v M w M B y 1 y L 1 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT SOT MO EUROPEN PROJETION ISSUE DTE Fig 13. Package outline SOT762-1 (DHVFN14) _6 Product data sheet Rev June of 16

14 13. bbreviations Table 10. cronym DM DUT ESD HBM TTL bbreviations Description harged Device Model Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status hange notice Supersedes _ Product data sheet - _5 Modifications: hange of hold time in Table Dynamic characteristics. Minimum values changed to 1.0 ns. _ Product data sheet - _4 _ Product specification - _3 _ Product specification - _2 _ Product specification - _1 _ Product specification - - _6 Product data sheet Rev June of 16

15 15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet ualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IE 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the haracteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 16. ontact information For additional information, please visit: For sales office addresses, send an to: salesaddresses@nxp.com _6 Product data sheet Rev June of 16

16 17. ontents 1 General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks ontact information ontents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 4 June 2007 Document identifier: _6