74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.
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1 Quad 2-input NND gate Rev November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible with Low-power Schottky TTL (LSTTL). The provides a quad 2-input NND function. Input levels: For 74HC00: CMOS level For 74HCT00: TTL level ESD protection: HBM JESD22-4F exceeds 2000 V MM JESD22-5- exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +25 C Table. Ordering information Type number Package Temperature range Name Description Version 74HC00N 40 C to +25 C DIP4 plastic dual in-line package; 4 leads (300 mil) SOT27-74HCT00N 74HC00D 40 C to +25 C SO4 plastic small outline package; 4 leads; body width SOT08-74HCT00D 74HC00DB 40 C to +25 C SSOP4 3.9 mm plastic shrink small outline package; 4 leads; body SOT337-74HCT00DB 74HC00PW 40 C to +25 C TSSOP4 width 5.3 mm plastic thin shrink small outline package; 4 leads; SOT402-74HCT00PW 74HC00BQ 40 C to +25 C DHVQFN4 body width 4.4 mm plastic dual in-line compatible thermal enhanced very SOT762-74HCT00BQ thin quad flat package; no leads; 4 terminals; body mm
2 Quad 2-input NND gate 4. Functional diagram B 2 2B Y 2Y & & B 4 4B 3Y 8 4Y mna & & mna246 8 B Y mna2 Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5. Pinning 74HC00 74HCT00 terminal index area 74HC00 74HCT00 VCC B Y V CC 4B 4 B Y B 4 4Y 2 2B 2Y Y 3B 3 2B 2Y 5 GND () B 3 GND 7 8 3Y GND 3Y 00aal324 00aal323 Transparent top view () This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration DIP4, SO4 and (T)SSOP4 Fig 5. Pin configuration DHVQFN4 5.2 Pin description Table 2. Pin description Symbol Pin Description to 4, 4, 9, 2 data input B to 4B 2, 5, 0, 3 data input 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
3 Quad 2-input NND gate Table 2. Pin description continued Symbol Pin Description Y to 4Y 3, 6, 8, data output GND 7 ground (0 V) V CC 4 supply voltage 6. Functional description Table 3. Function table [] Input Output n nb ny L X H X L H H H L [] H = HIGH voltage level; L = LOW voltage level; X = don t care. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC +0.5 V [] - 20 m I OK output clamping current V O < 0.5 V or V O >V CC +0.5V [] - 20 m I O output current 0.5 V < V O < V CC +0.5V - 25 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature C P tot total power dissipation [2] DIP4 package mw SO4, (T)SSOP4 and DHVQFN4 packages mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP4 package: P tot derates linearly with 2 mw/k above 70 C. For SO4 package: P tot derates linearly with 8 mw/k above 70 C. For (T)SSOP4 packages: P tot derates linearly with 5.5 mw/k above 60 C. For DHVQFN4 packages: P tot derates linearly with 4.5 mw/k above 60 C. 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
4 Quad 2-input NND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC00 74HCT00 Unit Min Typ Max Min Typ Max V CC supply voltage V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature C t/ V input transition rise and fall rate V CC = 2.0 V ns/v V CC = 4.5 V ns/v V CC = 6.0 V ns/v 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max 74HC00 V IH HIGH-level V CC = 2.0 V V input voltage V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level V CC = 2.0 V V input voltage V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 20 ; V CC = 2.0 V V I O = 20 ; V CC = 4.5 V V I O = 20 ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V OL LOW-level output voltage V I = V IH or V IL I O = 20 ; V CC = 2.0 V V I O = 20 ; V CC = 4.5 V V I O = 20 ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I I input leakage V I = V CC or GND; current V CC =6.0V I CC supply current V I = V CC or GND; I O =0; V CC =6.0V HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
5 Quad 2-input NND gate Table 6. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max C I input pf capacitance 74HCT00 V IH HIGH-level V CC = 4.5 V to 5.5 V V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = V I O = 4.0 m V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 ; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I I input leakage V I = V CC or GND; current V CC =6.0V I CC supply current V I = V CC or GND; I O =0; V CC =6.0V I CC C I additional supply current input capacitance per input pin; V I =V CC 2. V; I O =0; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V 0. Dynamic characteristics pf Table 7. Dynamic characteristics GND = 0 V; C L = 50 pf; for load circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +25 C Unit Min Typ Max Max (85 C) Max (25 C) 74HC00 t pd propagation delay n, nb to ny; see Figure 6 [] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; C L =5pF ns V CC = 6.0 V ns t t transition time see Figure 6 [2] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
6 Quad 2-input NND gate Table 7. Dynamic characteristics continued GND = 0 V; C L = 50 pf; for load circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +25 C Unit C PD power dissipation per package; V I =GNDtoV CC [3] pf capacitance 74HCT00 t pd propagation delay n, nb to ny; see Figure 6 [] V CC = 4.5 V ns V CC = 5.0 V; C L =5pF ns t t transition time V CC = 4.5 V; see Figure 6 [2] ns C PD power dissipation capacitance [] t pd is the same as t PHL and t PLH. [2] t t is the same as t THL and t TLH. [3] C PD is used to determine the dynamic power dissipation (P D in W): P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs.. Waveforms per package; V I =GNDtoV CC.5 V Min Typ Max Max (85 C) Max (25 C) [3] pf V I n, nb input V M GND ny output V OH t PHL V Y V M V X t PLH V OL t THL t TLH 00aai84 Fig 6. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Input to output propagation delays Table 8. Measurement points Type Input Output V M V M V X V Y 74HC00 0.5V CC 0.5V CC 0.V CC 0.9V CC 74HCT00.3 V.3 V 0.V CC 0.9V CC 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
7 Quad 2-input NND gate V I 90 % negative pulse GND V M 0 % t f t W V M t r V I positive pulse 0 % GND t r 90 % V M t W t f V M V CC G VI DUT VO RT CL 00aah768 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = termination resistance should be equal to output impedance Z o of the pulse generator. C L = load capacitance including jig and probe capacitance. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test V I t r, t f C L 74HC00 V CC 6.0 ns 5 pf, 50 pf t PLH, t PHL 74HCT V 6.0 ns 5 pf, 50 pf t PLH, t PHL 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
8 Quad 2-input NND gate 2. Package outline DIP4: plastic dual in-line package; 4 leads (300 mil) SOT27- D M E seating plane 2 L Z 4 e b b 8 w M c (e ) M H pin index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 2 () () min. max. b b c D E e e L M E M H w () Z max Note. Plastic or metal protrusions of 0.25 mm (0.0 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT27-050G04 MO-00 SC Fig 8. Package outline SOT27- (DIP4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
9 Quad 2-input NND gate SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT08- D E X c y H E v M Z 4 8 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT08-076E06 MS Fig 9. Package outline SOT08- (SO4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
10 Quad 2-input NND gate SSOP4: plastic shrink small outline package; 4 leads; body width 5.3 mm SOT337- D E X c y H E v M Z 4 8 Q 2 ( ) 3 pin index 7 detail X L p L θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E () e H E L L p Q v w y Z() max mm θ o 8 o 0 Note. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337- MO Fig 0. Package outline SOT337- (SSOP4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
11 Quad 2-input NND gate TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 8 pin index 2 Q ( ) 3 θ 7 e b p w M detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE Fig. Package outline SOT402- (TSSOP4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November 200 of 6
12 Quad 2-input NND gate DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.85 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () Eh e e L v w y y mm Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 2. Package outline SOT762- (DHVQFN4) 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
13 Quad 2-input NND gate 3. bbreviations Table 0. cronym CMOS DUT ESD HBM LSTTL MM TTL bbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT00 v Product data sheet - 74HC_HCT00 v.4 Modifications: Figure note [] of Figure 5: changed. 74HC_HCT00 v Product data sheet - 74HC_HCT00 v.3 74HC_HCT00 v Product data sheet - 74HC_HCT00_CNV v.2 74HC_HCT00_CNV v Product specification HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
14 Quad 2-input NND gate 5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
15 Quad 2-input NND gate Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com 74HC_HCT00 ll information provided in this document is subject to legal disclaimers. NXP B.V ll rights reserved. Product data sheet Rev November of 6
16 Quad 2-input NND gate 7. Contents General description Features and benefits Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V ll rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 25 November 200 Document identifier: 74HC_HCT00
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Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
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Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
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Rev. 6 13 June 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a quad 2-input ND gate. Inputs include
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Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
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74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
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Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
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Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
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Rev. 04 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They
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Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable
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Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 3 9 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable
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Rev. 6 1 February 2016 Product data sheet 1. General description The is a dual 4-bit multiplexer, each with four binary inputs (ni0 to ni3), an output enable input (noe) and shared select inputs (S0 and
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
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Rev. 5 7 ugust 202 Product data sheet. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
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Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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